target-alpha: Implement cvtql inline.
It's a simple mask and shift sequence. Also, fix a typo in the actual masks used. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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0c287402a8
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@ -95,10 +95,6 @@ DEF_HELPER_FLAGS_1(cvttq, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvttq_c, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvttq_c, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvttq_svic, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvttq_svic, TCG_CALL_CONST, i64, i64)
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DEF_HELPER_FLAGS_1(cvtql, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
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DEF_HELPER_1(cvtql_v, i64, i64)
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DEF_HELPER_1(cvtql_sv, i64, i64)
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DEF_HELPER_FLAGS_1(setroundmode, TCG_CALL_CONST, void, i32)
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DEF_HELPER_FLAGS_1(setroundmode, TCG_CALL_CONST, void, i32)
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DEF_HELPER_FLAGS_1(setflushzero, TCG_CALL_CONST, void, i32)
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DEF_HELPER_FLAGS_1(setflushzero, TCG_CALL_CONST, void, i32)
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DEF_HELPER_FLAGS_0(fp_exc_clear, TCG_CALL_CONST, void)
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DEF_HELPER_FLAGS_0(fp_exc_clear, TCG_CALL_CONST, void)
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@ -1203,26 +1203,6 @@ uint64_t helper_cvtlq (uint64_t a)
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return (lo & 0x3FFFFFFF) | (hi & 0xc0000000);
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return (lo & 0x3FFFFFFF) | (hi & 0xc0000000);
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}
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}
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uint64_t helper_cvtql (uint64_t a)
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{
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return ((a & 0xC0000000) << 32) | ((a & 0x7FFFFFFF) << 29);
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}
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uint64_t helper_cvtql_v (uint64_t a)
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{
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if ((int32_t)a != (int64_t)a)
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helper_excp(EXCP_ARITH, EXC_M_IOV);
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return helper_cvtql(a);
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}
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uint64_t helper_cvtql_sv (uint64_t a)
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{
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/* ??? I'm pretty sure there's nothing that /sv needs to do that /v
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doesn't do. The only thing I can think is that /sv is a valid
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instruction merely for completeness in the ISA. */
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return helper_cvtql_v(a);
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}
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/* PALcode support special instructions */
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/* PALcode support special instructions */
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#if !defined (CONFIG_USER_ONLY)
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#if !defined (CONFIG_USER_ONLY)
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void helper_hw_rei (void)
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void helper_hw_rei (void)
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@ -597,6 +597,41 @@ static inline void gen_fp_exc_raise(int rc, int fn11)
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gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
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gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
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}
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}
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static void gen_fcvtql(int rb, int rc)
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{
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if (unlikely(rc == 31)) {
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return;
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}
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if (unlikely(rb == 31)) {
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tcg_gen_movi_i64(cpu_fir[rc], 0);
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} else {
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TCGv tmp = tcg_temp_new();
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tcg_gen_andi_i64(tmp, cpu_fir[rb], 0xC0000000);
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tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rb], 0x3FFFFFFF);
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tcg_gen_shli_i64(tmp, tmp, 32);
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tcg_gen_shli_i64(cpu_fir[rc], cpu_fir[rc], 29);
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tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp);
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tcg_temp_free(tmp);
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}
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}
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static void gen_fcvtql_v(DisasContext *ctx, int rb, int rc)
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{
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if (rb != 31) {
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int lab = gen_new_label();
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TCGv tmp = tcg_temp_new();
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tcg_gen_ext32s_i64(tmp, cpu_fir[rb]);
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tcg_gen_brcond_i64(TCG_COND_EQ, tmp, cpu_fir[rb], lab);
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gen_excp(ctx, EXCP_ARITH, EXC_M_IOV);
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gen_set_label(lab);
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}
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gen_fcvtql(rb, rc);
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}
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#define FARITH2(name) \
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#define FARITH2(name) \
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static inline void glue(gen_f, name)(int rb, int rc) \
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static inline void glue(gen_f, name)(int rb, int rc) \
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{ \
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{ \
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@ -612,9 +647,6 @@ static inline void glue(gen_f, name)(int rb, int rc) \
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} \
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} \
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}
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}
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FARITH2(cvtlq)
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FARITH2(cvtlq)
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FARITH2(cvtql)
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FARITH2(cvtql_v)
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FARITH2(cvtql_sv)
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/* ??? VAX instruction qualifiers ignored. */
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/* ??? VAX instruction qualifiers ignored. */
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FARITH2(sqrtf)
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FARITH2(sqrtf)
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@ -2244,11 +2276,12 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
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break;
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break;
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case 0x130:
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case 0x130:
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/* CVTQL/V */
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/* CVTQL/V */
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gen_fcvtql_v(rb, rc);
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break;
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case 0x530:
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case 0x530:
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/* CVTQL/SV */
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/* CVTQL/SV */
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gen_fcvtql_sv(rb, rc);
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/* ??? I'm pretty sure there's nothing that /sv needs to do that
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/v doesn't do. The only thing I can think is that /sv is a
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valid instruction merely for completeness in the ISA. */
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gen_fcvtql_v(ctx, rb, rc);
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break;
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break;
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default:
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default:
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goto invalid_opc;
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goto invalid_opc;
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