aspeed: add a memory region for SRAM
The size of the SRAM depends on the SoC model, so use a per-soc definition when creating the region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-9-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -29,6 +29,7 @@
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#define ASPEED_SOC_VIC_BASE 0x1E6C0000
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#define ASPEED_SOC_VIC_BASE 0x1E6C0000
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#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
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#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
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#define ASPEED_SOC_SCU_BASE 0x1E6E2000
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#define ASPEED_SOC_SCU_BASE 0x1E6E2000
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#define ASPEED_SOC_SRAM_BASE 0x1E720000
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#define ASPEED_SOC_TIMER_BASE 0x1E782000
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#define ASPEED_SOC_TIMER_BASE 0x1E782000
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#define ASPEED_SOC_I2C_BASE 0x1E78A000
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#define ASPEED_SOC_I2C_BASE 0x1E78A000
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@ -47,15 +48,37 @@ static const char *aspeed_soc_ast2500_typenames[] = {
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"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
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"aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
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static const AspeedSoCInfo aspeed_socs[] = {
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static const AspeedSoCInfo aspeed_socs[] = {
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{ "ast2400-a0", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
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{
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1, aspeed_soc_ast2400_spi_bases,
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.name = "ast2400-a0",
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"aspeed.smc.fmc", aspeed_soc_ast2400_typenames },
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.cpu_model = "arm926",
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{ "ast2400", "arm926", AST2400_A0_SILICON_REV, AST2400_SDRAM_BASE,
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.silicon_rev = AST2400_A0_SILICON_REV,
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1, aspeed_soc_ast2400_spi_bases,
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.sdram_base = AST2400_SDRAM_BASE,
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"aspeed.smc.fmc", aspeed_soc_ast2400_typenames },
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.sram_size = 0x8000,
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{ "ast2500-a1", "arm1176", AST2500_A1_SILICON_REV, AST2500_SDRAM_BASE,
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.spis_num = 1,
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2, aspeed_soc_ast2500_spi_bases,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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"aspeed.smc.ast2500-fmc", aspeed_soc_ast2500_typenames },
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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}, {
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.name = "ast2400",
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.cpu_model = "arm926",
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.silicon_rev = AST2400_A0_SILICON_REV,
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.sdram_base = AST2400_SDRAM_BASE,
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.sram_size = 0x8000,
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.spis_num = 1,
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.spi_bases = aspeed_soc_ast2400_spi_bases,
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.fmc_typename = "aspeed.smc.fmc",
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.spi_typename = aspeed_soc_ast2400_typenames,
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}, {
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.name = "ast2500-a1",
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.cpu_model = "arm1176",
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.silicon_rev = AST2500_A1_SILICON_REV,
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.sdram_base = AST2500_SDRAM_BASE,
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.sram_size = 0x9000,
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.spis_num = 2,
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.spi_bases = aspeed_soc_ast2500_spi_bases,
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.fmc_typename = "aspeed.smc.ast2500-fmc",
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.spi_typename = aspeed_soc_ast2500_typenames,
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},
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};
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};
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/*
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/*
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@ -157,6 +180,17 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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/* SRAM */
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memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
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sc->info->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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vmstate_register_ram_global(&s->sram);
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memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
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&s->sram);
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/* VIC */
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/* VIC */
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
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if (err) {
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if (err) {
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@ -29,6 +29,7 @@ typedef struct AspeedSoCState {
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/*< public >*/
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/*< public >*/
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ARMCPU cpu;
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ARMCPU cpu;
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MemoryRegion iomem;
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MemoryRegion iomem;
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MemoryRegion sram;
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AspeedVICState vic;
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AspeedVICState vic;
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AspeedTimerCtrlState timerctrl;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedI2CState i2c;
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@ -46,6 +47,7 @@ typedef struct AspeedSoCInfo {
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const char *cpu_model;
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const char *cpu_model;
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uint32_t silicon_rev;
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uint32_t silicon_rev;
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hwaddr sdram_base;
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hwaddr sdram_base;
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uint64_t sram_size;
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int spis_num;
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int spis_num;
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const hwaddr *spi_bases;
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const hwaddr *spi_bases;
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const char *fmc_typename;
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const char *fmc_typename;
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