From 74b67e1f9de37f88e9a6062075ef647ae61d68df Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 20 Sep 2021 08:50:59 +0200 Subject: [PATCH] watchdog: aspeed: Fix sequential control writes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The logic in the handling for the control register required toggling the enable state for writes to stick. Rework the condition chain to allow sequential writes that do not update the enable state. Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model") Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Message-Id: <20210709053107.1829304-3-andrew@aj.id.au> Signed-off-by: Cédric Le Goater --- hw/watchdog/wdt_aspeed.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index faa3d35fdf..69c37af9a6 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -166,6 +166,8 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, } else if (!enable && aspeed_wdt_is_enabled(s)) { s->regs[WDT_CTRL] = data; timer_del(s->timer); + } else { + s->regs[WDT_CTRL] = data; } break; case WDT_RESET_WIDTH: