target/arm: Implement SVE2 SPLICE, EXT
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-48-richard.henderson@linaro.org Message-Id: <20200423180347.9403-1-steplong@quicinc.com> [rth: Rename the trans_* functions to *_sve2.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -494,10 +494,14 @@ CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
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### SVE Permute - Extract Group
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### SVE Permute - Extract Group
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# SVE extract vector (immediate offset)
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# SVE extract vector (destructive)
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EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
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EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
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&rrri rn=%reg_movprfx imm=%imm8_16_10
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&rrri rn=%reg_movprfx imm=%imm8_16_10
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# SVE2 extract vector (constructive)
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EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \
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&rri imm=%imm8_16_10
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### SVE Permute - Unpredicated Group
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### SVE Permute - Unpredicated Group
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# SVE broadcast general register
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# SVE broadcast general register
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@ -588,9 +592,12 @@ REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
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REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
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REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
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RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
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RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
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# SVE vector splice (predicated)
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# SVE vector splice (predicated, destructive)
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SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
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SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
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# SVE2 vector splice (predicated, constructive)
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SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn
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### SVE Select Vectors Group
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### SVE Select Vectors Group
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# SVE select vector elements (predicated)
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# SVE select vector elements (predicated)
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@ -2266,18 +2266,18 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
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*** SVE Permute Extract Group
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*** SVE Permute Extract Group
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*/
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*/
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static bool trans_EXT(DisasContext *s, arg_EXT *a)
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static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm)
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{
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{
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if (!sve_access_check(s)) {
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if (!sve_access_check(s)) {
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return true;
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return true;
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}
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}
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unsigned vsz = vec_full_reg_size(s);
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unsigned vsz = vec_full_reg_size(s);
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unsigned n_ofs = a->imm >= vsz ? 0 : a->imm;
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unsigned n_ofs = imm >= vsz ? 0 : imm;
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unsigned n_siz = vsz - n_ofs;
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unsigned n_siz = vsz - n_ofs;
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unsigned d = vec_full_reg_offset(s, a->rd);
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unsigned d = vec_full_reg_offset(s, rd);
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unsigned n = vec_full_reg_offset(s, a->rn);
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unsigned n = vec_full_reg_offset(s, rn);
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unsigned m = vec_full_reg_offset(s, a->rm);
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unsigned m = vec_full_reg_offset(s, rm);
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/* Use host vector move insns if we have appropriate sizes
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/* Use host vector move insns if we have appropriate sizes
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* and no unfortunate overlap.
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* and no unfortunate overlap.
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@ -2296,6 +2296,19 @@ static bool trans_EXT(DisasContext *s, arg_EXT *a)
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return true;
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return true;
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}
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}
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static bool trans_EXT(DisasContext *s, arg_EXT *a)
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{
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return do_EXT(s, a->rd, a->rn, a->rm, a->imm);
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}
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static bool trans_EXT_sve2(DisasContext *s, arg_rri *a)
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{
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if (!dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm);
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}
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/*
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/*
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*** SVE Permute - Unpredicated Group
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*** SVE Permute - Unpredicated Group
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*/
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*/
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@ -3013,6 +3026,18 @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
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return true;
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return true;
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}
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}
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static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
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{
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if (!dc_isar_feature(aa64_sve2, s)) {
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return false;
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}
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if (sve_access_check(s)) {
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gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
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a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
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}
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return true;
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}
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/*
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/*
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*** SVE Integer Compare - Vectors Group
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*** SVE Integer Compare - Vectors Group
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*/
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*/
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