aspeed: Support AST2600A1 silicon revision
There are minimal differences from Qemu's point of view between the A0 and A1 silicon revisions. As the A1 exercises different code paths in u-boot it is desirable to emulate that instead. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20200504093703.261135-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -93,7 +93,7 @@ struct AspeedBoardState {
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/* Tacoma hardware value */
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/* Tacoma hardware value */
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#define TACOMA_BMC_HW_STRAP1 0x00000000
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#define TACOMA_BMC_HW_STRAP1 0x00000000
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#define TACOMA_BMC_HW_STRAP2 0x00000000
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#define TACOMA_BMC_HW_STRAP2 0x00000040
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/*
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/*
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* The max ram region is for firmwares that scan the address space
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* The max ram region is for firmwares that scan the address space
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@ -585,7 +585,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
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mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
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amc->soc_name = "ast2600-a0";
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amc->soc_name = "ast2600-a1";
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amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
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amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
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amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
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amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
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amc->fmc_model = "w25q512jv";
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amc->fmc_model = "w25q512jv";
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@ -600,8 +600,8 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
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MachineClass *mc = MACHINE_CLASS(oc);
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MachineClass *mc = MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
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mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
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amc->soc_name = "ast2600-a0";
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amc->soc_name = "ast2600-a1";
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amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
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amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
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amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
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amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
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amc->fmc_model = "mx66l1g45g";
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amc->fmc_model = "mx66l1g45g";
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@ -557,9 +557,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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dc->realize = aspeed_soc_ast2600_realize;
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dc->realize = aspeed_soc_ast2600_realize;
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sc->name = "ast2600-a0";
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sc->name = "ast2600-a1";
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sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
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sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
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sc->silicon_rev = AST2600_A0_SILICON_REV;
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sc->silicon_rev = AST2600_A1_SILICON_REV;
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sc->sram_size = 0x10000;
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sc->sram_size = 0x10000;
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sc->spis_num = 2;
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sc->spis_num = 2;
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sc->ehcis_num = 2;
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sc->ehcis_num = 2;
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@ -571,7 +571,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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}
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}
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static const TypeInfo aspeed_soc_ast2600_type_info = {
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static const TypeInfo aspeed_soc_ast2600_type_info = {
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.name = "ast2600-a0",
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.name = "ast2600-a1",
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.parent = TYPE_ASPEED_SOC,
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.parent = TYPE_ASPEED_SOC,
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.instance_size = sizeof(AspeedSoCState),
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.instance_size = sizeof(AspeedSoCState),
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.instance_init = aspeed_soc_ast2600_init,
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.instance_init = aspeed_soc_ast2600_init,
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@ -431,6 +431,7 @@ static uint32_t aspeed_silicon_revs[] = {
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AST2500_A0_SILICON_REV,
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AST2500_A0_SILICON_REV,
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AST2500_A1_SILICON_REV,
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AST2500_A1_SILICON_REV,
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AST2600_A0_SILICON_REV,
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AST2600_A0_SILICON_REV,
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AST2600_A1_SILICON_REV,
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};
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};
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bool is_supported_silicon_rev(uint32_t silicon_rev)
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bool is_supported_silicon_rev(uint32_t silicon_rev)
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@ -649,12 +650,10 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = {
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.valid.unaligned = false,
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.valid.unaligned = false,
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};
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};
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static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = {
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static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
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[AST2600_SILICON_REV] = AST2600_SILICON_REV,
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[AST2600_SYS_RST_CTRL] = 0xF7C3FED8,
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[AST2600_SILICON_REV2] = AST2600_SILICON_REV,
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[AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100,
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[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
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[AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC,
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[AST2600_CLK_STOP_CTRL] = 0xEFF43E8B,
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[AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A,
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[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
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[AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0,
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[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
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[AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */
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[AST2600_HPLL_PARAM] = 0x1000405F,
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[AST2600_HPLL_PARAM] = 0x1000405F,
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@ -684,7 +683,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data)
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dc->desc = "ASPEED 2600 System Control Unit";
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dc->desc = "ASPEED 2600 System Control Unit";
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dc->reset = aspeed_ast2600_scu_reset;
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dc->reset = aspeed_ast2600_scu_reset;
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asc->resets = ast2600_a0_resets;
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asc->resets = ast2600_a1_resets;
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asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
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asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */
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asc->apb_divider = 4;
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asc->apb_divider = 4;
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asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
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asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS;
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@ -41,6 +41,7 @@ typedef struct AspeedSCUState {
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#define AST2500_A0_SILICON_REV 0x04000303U
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#define AST2500_A0_SILICON_REV 0x04000303U
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#define AST2500_A1_SILICON_REV 0x04010303U
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#define AST2500_A1_SILICON_REV 0x04010303U
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#define AST2600_A0_SILICON_REV 0x05000303U
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#define AST2600_A0_SILICON_REV 0x05000303U
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#define AST2600_A1_SILICON_REV 0x05010303U
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#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
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#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
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