target/xtensa: convert to do_transaction_failed
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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#else
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cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
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cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
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cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
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cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
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#endif
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cc->debug_excp_handler = xtensa_breakpoint_handler;
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cc->disas_set_info = xtensa_cpu_disas_set_info;
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@ -497,9 +497,10 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
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int mmu_idx);
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void xtensa_cpu_do_interrupt(CPUState *cpu);
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bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
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void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
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bool is_write, bool is_exec, int opaque,
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unsigned size);
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void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
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fprintf_function cpu_fprintf, int flags);
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hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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@ -566,7 +566,7 @@ static bool is_access_granted(unsigned access, int is_write)
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}
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}
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static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
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static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte);
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static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
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uint32_t vaddr, int is_write, int mmu_idx,
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@ -584,7 +584,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
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int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring);
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if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) &&
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may_lookup_pt && get_pte(env, vaddr, &pte) == 0) {
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may_lookup_pt && get_pte(env, vaddr, &pte)) {
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ring = (pte >> 4) & 0x3;
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wi = 0;
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split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei);
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@ -631,7 +631,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb,
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return 0;
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}
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static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
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static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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uint32_t paddr;
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@ -642,13 +642,29 @@ static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
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int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0,
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&paddr, &page_size, &access, false);
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qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n",
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__func__, vaddr, ret ? ~0 : paddr);
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if (ret == 0) {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: autorefill(%08x): PTE va = %08x, pa = %08x\n",
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__func__, vaddr, pt_vaddr, paddr);
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} else {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: autorefill(%08x): PTE va = %08x, failed (%d)\n",
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__func__, vaddr, pt_vaddr, ret);
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}
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if (ret == 0) {
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*pte = ldl_phys(cs->as, paddr);
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MemTxResult result;
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*pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED,
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&result);
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if (result != MEMTX_OK) {
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qemu_log_mask(CPU_LOG_MMU,
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"%s: couldn't load PTE: transaction failed (%u)\n",
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__func__, (unsigned)result);
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ret = 1;
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}
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return ret;
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}
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return ret == 0;
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}
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static int get_physical_addr_region(CPUXtensaState *env,
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@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int size,
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}
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}
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void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr,
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bool is_write, bool is_exec, int opaque,
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unsigned size)
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void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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CPUXtensaState *env = &cpu->env;
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cpu_restore_state(cs, retaddr, true);
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HELPER(exception_cause_vaddr)(env, env->pc,
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is_exec ?
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access_type == MMU_INST_FETCH ?
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INSTR_PIF_ADDR_ERROR_CAUSE :
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LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
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is_exec ? addr : cs->mem_io_vaddr);
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addr);
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}
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static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
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