target/sparc: Check for transaction failures in MXCC stream ASI accesses
Currently the ld/st_asi helper functions make calls to the ld*_phys() and st*_phys() functions for those ASIs which imply direct accesses to physical addresses. These implicitly rely on the unassigned_access hook to cause them to generate an MMU fault if the access fails. Switch to using the address_space_* functions instead, which return a MemTxResult that we can check. This means that when we switch SPARC over to using the do_transaction_failed hook we'll still get the same MMU faults we did before. This commit converts the ASIs which do MXCC stream source and destination accesses. It's not clear to me whether raising an MMU fault like this is the correct behaviour if we encounter a bus error, but we retain the same behaviour that the old unassigned_access hook would implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20190801183012.17564-4-peter.maydell@linaro.org
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@ -880,6 +880,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
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}
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break;
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case 0x01c00100: /* MXCC stream source */
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{
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int i;
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if (size == 8) {
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env->mxccregs[0] = val;
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} else {
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@ -887,20 +890,27 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
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"%08x: unimplemented access size: %d\n", addr,
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size);
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}
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env->mxccdata[0] = ldq_phys(cs->as,
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(env->mxccregs[0] & 0xffffffffULL) +
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0);
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env->mxccdata[1] = ldq_phys(cs->as,
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(env->mxccregs[0] & 0xffffffffULL) +
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8);
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env->mxccdata[2] = ldq_phys(cs->as,
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(env->mxccregs[0] & 0xffffffffULL) +
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16);
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env->mxccdata[3] = ldq_phys(cs->as,
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(env->mxccregs[0] & 0xffffffffULL) +
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24);
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for (i = 0; i < 4; i++) {
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MemTxResult result;
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hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i;
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env->mxccdata[i] = address_space_ldq(cs->as,
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access_addr,
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MEMTXATTRS_UNSPECIFIED,
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&result);
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if (result != MEMTX_OK) {
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/* TODO: investigate whether this is the right behaviour */
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sparc_raise_mmu_fault(cs, access_addr, false, false,
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false, size, GETPC());
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}
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}
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break;
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}
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case 0x01c00200: /* MXCC stream destination */
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{
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int i;
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if (size == 8) {
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env->mxccregs[1] = val;
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} else {
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@ -908,15 +918,22 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
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"%08x: unimplemented access size: %d\n", addr,
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size);
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}
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stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
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env->mxccdata[0]);
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stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
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env->mxccdata[1]);
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stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
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env->mxccdata[2]);
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stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
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env->mxccdata[3]);
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for (i = 0; i < 4; i++) {
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MemTxResult result;
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hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i;
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address_space_stq(cs->as, access_addr, env->mxccdata[i],
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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/* TODO: investigate whether this is the right behaviour */
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sparc_raise_mmu_fault(cs, access_addr, true, false,
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false, size, GETPC());
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}
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}
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break;
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}
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case 0x01c00a00: /* MXCC control register */
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if (size == 8) {
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env->mxccregs[3] = val;
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