fixed dirty bit support for 4M pages (L4 Pistachio fix)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@549 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -304,7 +304,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
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/* if PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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is_dirty = is_write && !(pde & PG_DIRTY_MASK);
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if (!(pde & PG_ACCESSED_MASK)) {
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK;
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if (is_dirty)
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pde |= PG_DIRTY_MASK;
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