openpic: Convert subregions to memory api
The "openpic" controller is currently using one big region and does subregion dispatching manually. Move this to the memory api. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
parent
a285f1ca70
commit
780d16b77f
106
hw/openpic.c
106
hw/openpic.c
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@ -79,6 +79,15 @@ enum {
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#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
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#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
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#endif
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#endif
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#define OPENPIC_GLB_REG_START 0x0
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#define OPENPIC_GLB_REG_SIZE 0x10F0
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#define OPENPIC_TMR_REG_START 0x10F0
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#define OPENPIC_TMR_REG_SIZE 0x220
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#define OPENPIC_SRC_REG_START 0x10000
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#define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
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#define OPENPIC_CPU_REG_START 0x20000
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#define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
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/* MPIC */
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/* MPIC */
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#define MPIC_MAX_CPU 1
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#define MPIC_MAX_CPU 1
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#define MPIC_MAX_EXT 12
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#define MPIC_MAX_EXT 12
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@ -842,53 +851,39 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
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return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
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return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
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}
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}
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static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
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static const MemoryRegionOps openpic_glb_ops = {
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unsigned len)
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.write = openpic_gbl_write,
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{
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.read = openpic_gbl_read,
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openpic_t *opp = opaque;
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
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static const MemoryRegionOps openpic_tmr_ops = {
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if (addr < 0x1100) {
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.write = openpic_timer_write,
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/* Global registers */
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.read = openpic_timer_read,
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openpic_gbl_write(opp, addr, val, len);
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.endianness = DEVICE_LITTLE_ENDIAN,
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} else if (addr < 0x10000) {
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.impl = {
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/* Timers registers */
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.min_access_size = 4,
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openpic_timer_write(opp, addr, val, len);
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.max_access_size = 4,
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} else if (addr < 0x20000) {
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},
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/* Source registers */
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};
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openpic_src_write(opp, addr, val, len);
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} else {
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/* CPU registers */
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openpic_cpu_write(opp, addr, val, len);
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}
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}
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static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
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static const MemoryRegionOps openpic_cpu_ops = {
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{
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.write = openpic_cpu_write,
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openpic_t *opp = opaque;
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.read = openpic_cpu_read,
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uint32_t retval;
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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DPRINTF("%s: offset %08x\n", __func__, (int)addr);
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static const MemoryRegionOps openpic_src_ops = {
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if (addr < 0x1100) {
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.write = openpic_src_write,
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/* Global registers */
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.read = openpic_src_read,
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retval = openpic_gbl_read(opp, addr, len);
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} else if (addr < 0x10000) {
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/* Timers registers */
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retval = openpic_timer_read(opp, addr, len);
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} else if (addr < 0x20000) {
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/* Source registers */
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retval = openpic_src_read(opp, addr, len);
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} else {
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/* CPU registers */
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retval = openpic_cpu_read(opp, addr, len);
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}
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return retval;
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}
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static const MemoryRegionOps openpic_ops = {
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.read = openpic_read,
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.write = openpic_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.impl = {
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.min_access_size = 4,
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.min_access_size = 4,
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@ -1009,12 +1004,33 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
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{
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{
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openpic_t *opp;
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openpic_t *opp;
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int i, m;
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int i, m;
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struct {
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const char *name;
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MemoryRegionOps const *ops;
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hwaddr start_addr;
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ram_addr_t size;
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} const list[] = {
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{"glb", &openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
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{"src", &openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
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{"cpu", &openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
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};
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/* XXX: for now, only one CPU is supported */
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/* XXX: for now, only one CPU is supported */
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if (nb_cpus != 1)
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if (nb_cpus != 1)
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return NULL;
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return NULL;
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opp = g_malloc0(sizeof(openpic_t));
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opp = g_malloc0(sizeof(openpic_t));
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memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000);
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memory_region_init(&opp->mem, "openpic", 0x40000);
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for (i = 0; i < ARRAY_SIZE(list); i++) {
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memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
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list[i].name, list[i].size);
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memory_region_add_subregion(&opp->mem, list[i].start_addr,
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&opp->sub_io_mem[i]);
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}
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// isu_base &= 0xFFFC0000;
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// isu_base &= 0xFFFC0000;
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opp->nb_cpus = nb_cpus;
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opp->nb_cpus = nb_cpus;
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