haraldwolff/qemu-patch-raspberry4
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

spapr: Fix typos in comments and macro indentation

Browse source 
This commit fixes typos in spapr_vio_reg_to_irq() comments and a macro
indentation.

Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
Message-Id: <1590710681-12873-1-git-send-email-gromero@linux.ibm.com>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Gustavo Romero 2020-05-28 20:04:41 -04:00 committed by David Gibson
parent a816f2d6b8
commit 7861e083f8
2 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
hw/ppc/spapr_vio.c
View file

@ -420,7 +420,7 @@ static void spapr_vio_busdev_reset(DeviceState *qdev)
}
/*
* The register property of a VIO device is defined in livirt using
* The register property of a VIO device is defined in libvirt using
* 0x1000 as a base register number plus a 0x1000 increment. For the
* VIO tty device, the base number is changed to 0x30000000. QEMU uses
* a base register number of 0x71000000 and then a simple increment.
@ -450,7 +450,7 @@ static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg)
} else if (reg >= 0x30000000) {
/*
* VIO tty devices register values, when allocated by livirt,
* VIO tty devices register values, when allocated by libvirt,
* are mapped in range [0xf0 - 0xff], gives us a maximum of 16
* vtys.
*/
@ -459,7 +459,7 @@ static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg)
} else {
/*
* Other VIO devices register values, when allocated by
* livirt, should be mapped in range [0x00 - 0xef]. Conflicts
* libvirt, should be mapped in range [0x00 - 0xef]. Conflicts
* will be detected when IRQ is claimed.
*/
irq = (reg >> 12) & 0xff;

2
include/hw/ppc/xive_regs.h
View file

@ -71,7 +71,7 @@
* QW word 2 contains the valid bit at the top and other fields
* depending on the QW.
*/
#define TM_WORD2 0x8
#define TM_WORD2 0x8
#define TM_QW0W2_VU PPC_BIT32(0)
#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1, 31) /* XX 2,31 ? */
#define TM_QW1W2_VO PPC_BIT32(0)