target/arm: Declare some M-profile functions publicly
In the next commit we will split the M-profile functions from this file. Some function will be called out of helper.c. Declare them in the "internals.h" header. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-22-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -39,21 +39,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
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target_ulong *page_size_ptr,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
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/* Security attributes for an address, as returned by v8m_security_lookup. */
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typedef struct V8M_SAttributes {
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bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
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bool ns;
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bool nsc;
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uint8_t sregion;
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bool srvalid;
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uint8_t iregion;
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bool irvalid;
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} V8M_SAttributes;
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static void v8m_security_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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V8M_SAttributes *sattrs);
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#endif
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static void switch_mode(CPUARMState *env, int mode);
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@ -7733,25 +7718,6 @@ void arm_log_exception(int idx)
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}
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}
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/*
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* Return true if the v7M CPACR permits access to the FPU for the specified
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* security state and privilege level.
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*/
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static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv)
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{
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switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
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case 0:
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case 2: /* UNPREDICTABLE: we treat like 0 */
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return false;
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case 1:
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return is_priv;
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case 3:
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return true;
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default:
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g_assert_not_reached();
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}
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}
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/*
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* What kind of stack write are we doing? This affects how exceptions
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* generated during the stacking are treated.
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@ -12117,7 +12083,7 @@ static bool v8m_is_sau_exempt(CPUARMState *env,
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(address >= 0xe00ff000 && address <= 0xe00fffff);
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}
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static void v8m_security_lookup(CPUARMState *env, uint32_t address,
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void v8m_security_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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V8M_SAttributes *sattrs)
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{
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@ -12224,7 +12190,7 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
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}
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}
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static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, bool *is_subpage,
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@ -892,6 +892,27 @@ static inline uint32_t v7m_sp_limit(CPUARMState *env)
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}
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}
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/**
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* v7m_cpacr_pass:
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* Return true if the v7M CPACR permits access to the FPU for the specified
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* security state and privilege level.
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*/
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static inline bool v7m_cpacr_pass(CPUARMState *env,
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bool is_secure, bool is_priv)
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{
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switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
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case 0:
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case 2: /* UNPREDICTABLE: we treat like 0 */
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return false;
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case 1:
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return is_priv;
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case 3:
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return true;
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default:
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g_assert_not_reached();
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}
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}
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/**
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* aarch32_mode_name(): Return name of the AArch32 CPU mode
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* @psr: Program Status Register indicating CPU mode
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@ -988,6 +1009,27 @@ static inline int exception_target_el(CPUARMState *env)
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#ifndef CONFIG_USER_ONLY
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/* Security attributes for an address, as returned by v8m_security_lookup. */
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typedef struct V8M_SAttributes {
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bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
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bool ns;
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bool nsc;
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uint8_t sregion;
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bool srvalid;
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uint8_t iregion;
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bool irvalid;
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} V8M_SAttributes;
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void v8m_security_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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V8M_SAttributes *sattrs);
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bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, bool *is_subpage,
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ARMMMUFaultInfo *fi, uint32_t *mregion);
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/* Cacheability and shareability attributes for a memory access */
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typedef struct ARMCacheAttrs {
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unsigned int attrs:8; /* as in the MAIR register encoding */
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