target/arm: Implement SVE copy to vector (predicated)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180613015641.5667-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -450,6 +450,12 @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
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LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
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LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
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# SVE copy element from SIMD&FP scalar register
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CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
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# SVE copy element from general register to vector (predicated)
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CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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@ -2624,6 +2624,25 @@ static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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return do_last_general(s, a, true);
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}
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static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn));
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}
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return true;
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}
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static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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if (sve_access_check(s)) {
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int ofs = vec_reg_offset(s, a->rn, 0, a->esz);
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TCGv_i64 t = load_esz(cpu_env, ofs, a->esz);
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do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);
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tcg_temp_free_i64(t);
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}
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return true;
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}
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/*
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*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
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*/
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