qemu-sparc queue
-----BEGIN PGP SIGNATURE----- iQFSBAABCAA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAlsn7zweHG1hcmsuY2F2 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfwZwH/2Rq5qG+OHdY13wv vanFNbRRsBSXhxO7+E9zggGAtCbFpWq54GhbNUDppK0z3JKlLE6T0gtNBTSGVrew LiXicYAAzTJSqOYq10Ke8frKYqW6Ap+ANR87v1ab0q3nofeOmRVDguMLF7iD8FYP 6yNiSOHdOp4WB7oZl6MuxzFYLDqxc499WZbRJOqUx+K4W1B95B4l2z1y8II/CRVB uhIkBo3oivYmZV8aLG+uIeRJUmFFSDU5c6bdNeQ35rDgijfBetWfj5rHV7PxbNIw h6vysuUIoDMX3rygKeAtETGpFMF9hGdK0CHse9CfT0kZGA2ZrauEWRwGismX9qcj rYxRGFM= =Z3ee -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20180618' into staging qemu-sparc queue # gpg: Signature made Mon 18 Jun 2018 18:43:24 BST # gpg: using RSA key 5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20180618: SPARC64: add icount support hw/sparc/sun4m: Fix problems with device introspection hw/sparc64/sun4u: Fix introspection by converting prom instance_init to realize Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
79449bc311
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@ -572,23 +572,36 @@ typedef struct IDRegState {
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MemoryRegion mem;
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} IDRegState;
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static void idreg_init1(Object *obj)
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static void idreg_realize(DeviceState *ds, Error **errp)
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{
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IDRegState *s = MACIO_ID_REGISTER(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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IDRegState *s = MACIO_ID_REGISTER(ds);
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SysBusDevice *dev = SYS_BUS_DEVICE(ds);
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Error *local_err = NULL;
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memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
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sizeof(idreg_data), &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_ram_nomigrate(&s->mem, obj,
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"sun4m.idreg", sizeof(idreg_data), &error_fatal);
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vmstate_register_ram_global(&s->mem);
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memory_region_set_readonly(&s->mem, true);
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sysbus_init_mmio(dev, &s->mem);
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}
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static void idreg_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = idreg_realize;
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}
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static const TypeInfo idreg_info = {
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.name = TYPE_MACIO_ID_REGISTER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IDRegState),
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.instance_init = idreg_init1,
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.class_init = idreg_class_init,
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};
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#define TYPE_TCX_AFX "tcx_afx"
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@ -613,21 +626,35 @@ static void afx_init(hwaddr addr)
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sysbus_mmio_map(s, 0, addr);
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}
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static void afx_init1(Object *obj)
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static void afx_realize(DeviceState *ds, Error **errp)
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{
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AFXState *s = TCX_AFX(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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AFXState *s = TCX_AFX(ds);
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SysBusDevice *dev = SYS_BUS_DEVICE(ds);
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Error *local_err = NULL;
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memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
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&local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
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vmstate_register_ram_global(&s->mem);
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sysbus_init_mmio(dev, &s->mem);
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}
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static void afx_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = afx_realize;
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}
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static const TypeInfo afx_info = {
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.name = TYPE_TCX_AFX,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AFXState),
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.instance_init = afx_init1,
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.class_init = afx_class_init,
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};
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#define TYPE_OPENPROM "openprom"
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@ -680,13 +707,19 @@ static void prom_init(hwaddr addr, const char *bios_name)
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}
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}
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static void prom_init1(Object *obj)
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static void prom_realize(DeviceState *ds, Error **errp)
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{
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PROMState *s = OPENPROM(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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PROMState *s = OPENPROM(ds);
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SysBusDevice *dev = SYS_BUS_DEVICE(ds);
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Error *local_err = NULL;
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memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
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PROM_SIZE_MAX, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
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&error_fatal);
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vmstate_register_ram_global(&s->prom);
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memory_region_set_readonly(&s->prom, true);
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sysbus_init_mmio(dev, &s->prom);
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@ -701,6 +734,7 @@ static void prom_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = prom_properties;
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dc->realize = prom_realize;
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}
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static const TypeInfo prom_info = {
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@ -708,7 +742,6 @@ static const TypeInfo prom_info = {
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PROMState),
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.class_init = prom_class_init,
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.instance_init = prom_init1,
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};
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#define TYPE_SUN4M_MEMORY "memory"
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@ -425,13 +425,19 @@ static void prom_init(hwaddr addr, const char *bios_name)
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}
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}
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static void prom_init1(Object *obj)
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static void prom_realize(DeviceState *ds, Error **errp)
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{
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PROMState *s = OPENPROM(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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PROMState *s = OPENPROM(ds);
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SysBusDevice *dev = SYS_BUS_DEVICE(ds);
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Error *local_err = NULL;
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memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
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PROM_SIZE_MAX, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
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&error_fatal);
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vmstate_register_ram_global(&s->prom);
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memory_region_set_readonly(&s->prom, true);
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sysbus_init_mmio(dev, &s->prom);
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@ -446,6 +452,7 @@ static void prom_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = prom_properties;
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dc->realize = prom_realize;
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}
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static const TypeInfo prom_info = {
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@ -453,7 +460,6 @@ static const TypeInfo prom_info = {
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PROMState),
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.class_init = prom_class_init,
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.instance_init = prom_init1,
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};
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@ -41,6 +41,8 @@
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#define JUMP_PC 2 /* dynamic pc value which takes only two values
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according to jump_pc[T2] */
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#define DISAS_EXIT DISAS_TARGET_0
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/* global register indexes */
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static TCGv_ptr cpu_regwptr;
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static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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@ -3400,11 +3402,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_const = tcg_const_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, tick));
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
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r_const);
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tcg_temp_free_ptr(r_tickptr);
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tcg_temp_free_i32(r_const);
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gen_store_gpr(dc, rd, cpu_dst);
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_end();
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}
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}
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break;
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case 0x5: /* V9 rdpc */
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@ -3447,11 +3455,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_const = tcg_const_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, stick));
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
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r_const);
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tcg_temp_free_ptr(r_tickptr);
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tcg_temp_free_i32(r_const);
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gen_store_gpr(dc, rd, cpu_dst);
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_end();
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}
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}
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break;
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case 0x19: /* System tick compare */
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@ -3576,10 +3590,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_const = tcg_const_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, tick));
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_get_count(cpu_tmp0, cpu_env,
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r_tickptr, r_const);
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tcg_temp_free_ptr(r_tickptr);
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tcg_temp_free_i32(r_const);
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_end();
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}
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}
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break;
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case 5: // tba
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@ -4385,9 +4405,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, tick));
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_set_limit(r_tickptr,
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cpu_tick_cmpr);
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tcg_temp_free_ptr(r_tickptr);
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_end();
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}
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/* End TB to handle timer interrupt */
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dc->base.is_jmp = DISAS_EXIT;
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}
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break;
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case 0x18: /* System tick */
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@ -4403,9 +4433,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, stick));
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_set_count(r_tickptr,
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cpu_tmp0);
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tcg_temp_free_ptr(r_tickptr);
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_end();
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}
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/* End TB to handle timer interrupt */
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dc->base.is_jmp = DISAS_EXIT;
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}
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break;
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case 0x19: /* System tick compare */
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@ -4421,9 +4461,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, stick));
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_set_limit(r_tickptr,
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cpu_stick_cmpr);
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tcg_temp_free_ptr(r_tickptr);
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_end();
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}
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/* End TB to handle timer interrupt */
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dc->base.is_jmp = DISAS_EXIT;
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}
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break;
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@ -4531,9 +4581,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, tick));
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_tick_set_count(r_tickptr,
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cpu_tmp0);
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tcg_temp_free_ptr(r_tickptr);
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if (tb_cflags(dc->base.tb) &
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CF_USE_ICOUNT) {
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gen_io_end();
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}
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/* End TB to handle timer interrupt */
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dc->base.is_jmp = DISAS_EXIT;
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}
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break;
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case 5: // tba
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@ -4541,7 +4601,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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break;
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case 6: // pstate
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save_state(dc);
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_wrpstate(cpu_env, cpu_tmp0);
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_end();
|
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}
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dc->npc = DYNAMIC_PC;
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break;
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case 7: // tl
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|
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@ -4551,7 +4617,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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dc->npc = DYNAMIC_PC;
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break;
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case 8: // pil
|
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
|
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gen_io_start();
|
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}
|
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gen_helper_wrpil(cpu_env, cpu_tmp0);
|
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
|
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gen_io_end();
|
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}
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break;
|
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case 9: // cwp
|
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gen_helper_wrcwp(cpu_env, cpu_tmp0);
|
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|
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@ -4642,9 +4714,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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r_tickptr = tcg_temp_new_ptr();
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
|
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offsetof(CPUSPARCState, hstick));
|
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if (tb_cflags(dc->base.tb) &
|
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CF_USE_ICOUNT) {
|
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gen_io_start();
|
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}
|
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gen_helper_tick_set_limit(r_tickptr,
|
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cpu_hstick_cmpr);
|
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tcg_temp_free_ptr(r_tickptr);
|
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if (tb_cflags(dc->base.tb) &
|
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CF_USE_ICOUNT) {
|
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gen_io_end();
|
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}
|
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/* End TB to handle timer interrupt */
|
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dc->base.is_jmp = DISAS_EXIT;
|
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}
|
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break;
|
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case 6: // hver readonly
|
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|
|
@ -5265,14 +5347,26 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
|
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goto priv_insn;
|
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dc->npc = DYNAMIC_PC;
|
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dc->pc = DYNAMIC_PC;
|
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
|
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gen_io_start();
|
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}
|
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gen_helper_done(cpu_env);
|
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
|
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gen_io_end();
|
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}
|
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goto jmp_insn;
|
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case 1:
|
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if (!supervisor(dc))
|
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goto priv_insn;
|
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dc->npc = DYNAMIC_PC;
|
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dc->pc = DYNAMIC_PC;
|
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
|
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gen_io_start();
|
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}
|
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gen_helper_retry(cpu_env);
|
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
|
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gen_io_end();
|
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}
|
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goto jmp_insn;
|
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default:
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goto illegal_insn;
|
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|
|
@ -5822,7 +5916,9 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
|
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{
|
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DisasContext *dc = container_of(dcbase, DisasContext, base);
|
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|
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if (dc->base.is_jmp != DISAS_NORETURN) {
|
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switch (dc->base.is_jmp) {
|
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case DISAS_NEXT:
|
||||
case DISAS_TOO_MANY:
|
||||
if (dc->pc != DYNAMIC_PC &&
|
||||
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
|
||||
/* static PC and NPC: we can use direct chaining */
|
||||
|
|
@ -5834,6 +5930,19 @@ static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
|
|||
save_npc(dc);
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
}
|
||||
break;
|
||||
|
||||
case DISAS_NORETURN:
|
||||
break;
|
||||
|
||||
case DISAS_EXIT:
|
||||
/* Exit TB */
|
||||
save_state(dc);
|
||||
tcg_gen_exit_tb(NULL, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue