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hw/intc/arm_gic: Fix handling of GICD_ITARGETSR

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The GICD_ITARGETSR implementation still has some 11MPCore behaviour
that we were incorrectly using in our GICv1 and GICv2 implementations
for the case where the interrupt number is less than GIC_INTERNAL.
The desired behaviour here is:
 * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the
   CPU doing the read for irqs 29..31
 * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a
   number matching the CPU doing the read for all irqs < 32

Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this
is an 11MPCore GIC.

Reported-by: Jan Kiszka <jan.kiszka@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180712154152.32183-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2018-07-16 17:18:41 +01:00
parent ee03cca88e
commit 7995206d05
1 changed files with 4 additions and 2 deletions
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6
hw/intc/arm_gic.c
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@ -751,7 +751,9 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
if (irq >= s->num_irq) {
goto bad_reg;
}
if (irq >= 29 && irq <= 31) {
if (irq < 29 && s->revision == REV_11MPCORE) {
res = 0;
} else if (irq < GIC_INTERNAL) {
res = cm;
} else {
res = GIC_TARGET(irq);
@ -1014,7 +1016,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
if (irq >= s->num_irq) {
goto bad_reg;
}
if (irq < 29) {
if (irq < 29 && s->revision == REV_11MPCORE) {
value = 0;
} else if (irq < GIC_INTERNAL) {
value = ALL_CPU_MASK;