hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
The GICD_ITARGETSR implementation still has some 11MPCore behaviour that we were incorrectly using in our GICv1 and GICv2 implementations for the case where the interrupt number is less than GIC_INTERNAL. The desired behaviour here is: * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the CPU doing the read for irqs 29..31 * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a number matching the CPU doing the read for all irqs < 32 Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this is an 11MPCore GIC. Reported-by: Jan Kiszka <jan.kiszka@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180712154152.32183-3-peter.maydell@linaro.org
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@ -751,7 +751,9 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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if (irq >= 29 && irq <= 31) {
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if (irq < 29 && s->revision == REV_11MPCORE) {
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res = 0;
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} else if (irq < GIC_INTERNAL) {
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res = cm;
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} else {
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res = GIC_TARGET(irq);
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@ -1014,7 +1016,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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if (irq < 29) {
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if (irq < 29 && s->revision == REV_11MPCORE) {
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value = 0;
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} else if (irq < GIC_INTERNAL) {
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value = ALL_CPU_MASK;
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