target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
gvec should provide vecop_list to avoid: "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200710104920.13550-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -958,22 +958,27 @@ static void gen_rsub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
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static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
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static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
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TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
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TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
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{
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{
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static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
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static const GVecGen2s rsub_op[4] = {
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static const GVecGen2s rsub_op[4] = {
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{ .fni8 = gen_vec_rsub8_i64,
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{ .fni8 = gen_vec_rsub8_i64,
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.fniv = gen_rsub_vec,
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.fniv = gen_rsub_vec,
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.fno = gen_helper_vec_rsubs8,
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.fno = gen_helper_vec_rsubs8,
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.opt_opc = vecop_list,
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.vece = MO_8 },
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.vece = MO_8 },
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{ .fni8 = gen_vec_rsub16_i64,
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{ .fni8 = gen_vec_rsub16_i64,
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.fniv = gen_rsub_vec,
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.fniv = gen_rsub_vec,
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.fno = gen_helper_vec_rsubs16,
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.fno = gen_helper_vec_rsubs16,
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.opt_opc = vecop_list,
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.vece = MO_16 },
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.vece = MO_16 },
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{ .fni4 = gen_rsub_i32,
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{ .fni4 = gen_rsub_i32,
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.fniv = gen_rsub_vec,
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.fniv = gen_rsub_vec,
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.fno = gen_helper_vec_rsubs32,
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.fno = gen_helper_vec_rsubs32,
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.opt_opc = vecop_list,
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.vece = MO_32 },
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.vece = MO_32 },
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{ .fni8 = gen_rsub_i64,
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{ .fni8 = gen_rsub_i64,
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.fniv = gen_rsub_vec,
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.fniv = gen_rsub_vec,
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.fno = gen_helper_vec_rsubs64,
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.fno = gen_helper_vec_rsubs64,
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.opt_opc = vecop_list,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.vece = MO_64 },
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.vece = MO_64 },
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};
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};
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