xilinx_zynq: added QSPI controller
Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow modelling of the different geometries. E.G. Dual parallel and dual stacked mode can both be tested with this one arrangement. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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@ -27,6 +27,8 @@
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#include "ssi.h"
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#include "ssi.h"
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#define NUM_SPI_FLASHES 4
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#define NUM_SPI_FLASHES 4
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#define NUM_QSPI_FLASHES 2
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#define NUM_QSPI_BUSSES 2
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#define FLASH_SIZE (64 * 1024 * 1024)
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#define FLASH_SIZE (64 * 1024 * 1024)
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#define FLASH_SECTOR_SIZE (128 * 1024)
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#define FLASH_SECTOR_SIZE (128 * 1024)
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@ -49,30 +51,43 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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sysbus_connect_irq(s, 0, irq);
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sysbus_connect_irq(s, 0, irq);
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}
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}
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static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq)
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static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
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bool is_qspi)
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{
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{
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DeviceState *dev;
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DeviceState *dev;
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SysBusDevice *busdev;
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SysBusDevice *busdev;
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SSIBus *spi;
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SSIBus *spi;
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int i;
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int i, j;
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int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
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int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
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dev = qdev_create(NULL, "xilinx,spips");
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dev = qdev_create(NULL, "xilinx,spips");
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qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
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qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
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qdev_prop_set_uint8(dev, "num-busses", num_busses);
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qdev_init_nofail(dev);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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busdev = sysbus_from_qdev(dev);
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sysbus_mmio_map(busdev, 0, base_addr);
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sysbus_mmio_map(busdev, 0, base_addr);
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if (is_qspi) {
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sysbus_mmio_map(busdev, 1, 0xFC000000);
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}
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sysbus_connect_irq(busdev, 0, irq);
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sysbus_connect_irq(busdev, 0, irq);
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spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
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for (i = 0; i < num_busses; ++i) {
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char bus_name[16];
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for (i = 0; i < NUM_SPI_FLASHES; ++i) {
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qemu_irq cs_line;
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qemu_irq cs_line;
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dev = ssi_create_slave_no_init(spi, "m25p80");
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snprintf(bus_name, 16, "spi%d", i);
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qdev_prop_set_string(dev, "partname", "n25q128");
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spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
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qdev_init_nofail(dev);
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cs_line = qdev_get_gpio_in(dev, 0);
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for (j = 0; j < num_ss; ++j) {
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sysbus_connect_irq(busdev, i+1, cs_line);
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dev = ssi_create_slave_no_init(spi, "m25p80");
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qdev_prop_set_string(dev, "partname", "n25q128");
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qdev_init_nofail(dev);
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cs_line = qdev_get_gpio_in(dev, 0);
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sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
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}
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}
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}
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}
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}
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@ -147,8 +162,9 @@ static void zynq_init(QEMUMachineInitArgs *args)
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pic[n] = qdev_get_gpio_in(dev, n);
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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}
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zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]);
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zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
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zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]);
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zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
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zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
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sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
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sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
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sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
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sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
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