riscv: sifive_u: Fix broken GEM support
At present the GEM support in sifive_u machine is seriously broken. The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using create_unimplemented_device(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the <reg> property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -19,6 +19,7 @@ config SIFIVE_U
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select CADENCE
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select HART
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select SIFIVE
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select UNIMP
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config SPIKE
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bool
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@ -3,6 +3,7 @@
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* Provides a board compatible with the SiFive Freedom U SDK:
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*
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@ -11,6 +12,7 @@
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* 2) PLIC (Platform Level Interrupt Controller)
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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* 4) OTP (One-Time Programmable) memory with stored serial number
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* 5) GEM (Gigabit Ethernet Controller) and management block
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*
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* This board currently generates devicetree dynamically that indicates at least
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* two harts and up to five harts.
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@ -37,6 +39,7 @@
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/cpu/cluster.h"
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#include "hw/misc/unimp.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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@ -45,6 +48,7 @@
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#include "hw/riscv/sifive_u.h"
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#include "hw/riscv/boot.h"
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#include "chardev/char.h"
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#include "net/eth.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/sysemu.h"
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@ -67,7 +71,8 @@ static const struct MemmapEntry {
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[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
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[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
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[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
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[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
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};
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#define OTP_SERIAL 1
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@ -84,7 +89,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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char ethclk_names[] = "pclk\0hclk";
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uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
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uint32_t uartclk_phandle;
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uint32_t hfclk_phandle, rtcclk_phandle;
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uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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@ -254,21 +259,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(nodename);
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phy_phandle = phandle++;
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nodename = g_strdup_printf("/soc/ethernet@%lx",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
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qemu_fdt_setprop_string(fdt, nodename, "compatible",
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"sifive,fu540-c000-gem");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GEM].base,
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0x0, memmap[SIFIVE_U_GEM].size);
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0x0, memmap[SIFIVE_U_GEM].size,
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0x0, memmap[SIFIVE_U_GEM_MGMT].base,
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0x0, memmap[SIFIVE_U_GEM_MGMT].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
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qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
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qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
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sizeof(ethclk_names));
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qemu_fdt_setprop(fdt, nodename, "local-mac-address",
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s->soc.gem.conf.macaddr.a, ETH_ALEN);
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qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
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qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
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g_free(nodename);
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@ -276,6 +288,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
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qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
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g_free(nodename);
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@ -525,6 +538,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
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plic_gpios[SIFIVE_U_GEM_IRQ]);
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create_unimplemented_device("riscv.sifive.u.gem-mgmt",
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memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
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}
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static void riscv_sifive_u_machine_init(MachineClass *mc)
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@ -64,7 +64,8 @@ enum {
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SIFIVE_U_UART1,
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SIFIVE_U_OTP,
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SIFIVE_U_DRAM,
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SIFIVE_U_GEM
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SIFIVE_U_GEM,
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SIFIVE_U_GEM_MGMT
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};
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enum {
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