target/mips: Fix block-comment-related issues in msa_helper.c
Fix block-comment-related issues reported by checkpatch for file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -1975,8 +1975,10 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
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c &= ~FP_UNDERFLOW;
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c &= ~FP_UNDERFLOW;
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}
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}
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/* Reciprocal operations set only Inexact when valid and not
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/*
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divide by zero */
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* Reciprocal operations set only Inexact when valid and not
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* divide by zero
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*/
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if ((action & RECIPROCAL_INEXACT) &&
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if ((action & RECIPROCAL_INEXACT) &&
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(c & (FP_INVALID | FP_DIV0)) == 0) {
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(c & (FP_INVALID | FP_DIV0)) == 0) {
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c = FP_INEXACT;
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c = FP_INEXACT;
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@ -1985,15 +1987,19 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
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cause = c & enable; /* all current enabled exceptions */
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cause = c & enable; /* all current enabled exceptions */
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if (cause == 0) {
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if (cause == 0) {
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/* No enabled exception, update the MSACSR Cause
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/*
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with all current exceptions */
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* No enabled exception, update the MSACSR Cause
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* with all current exceptions
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*/
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SET_FP_CAUSE(env->active_tc.msacsr,
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SET_FP_CAUSE(env->active_tc.msacsr,
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(GET_FP_CAUSE(env->active_tc.msacsr) | c));
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(GET_FP_CAUSE(env->active_tc.msacsr) | c));
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} else {
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} else {
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/* Current exceptions are enabled */
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/* Current exceptions are enabled */
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if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
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if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
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/* Exception(s) will trap, update MSACSR Cause
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/*
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with all enabled exceptions */
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* Exception(s) will trap, update MSACSR Cause
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* with all enabled exceptions
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*/
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SET_FP_CAUSE(env->active_tc.msacsr,
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SET_FP_CAUSE(env->active_tc.msacsr,
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(GET_FP_CAUSE(env->active_tc.msacsr) | c));
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(GET_FP_CAUSE(env->active_tc.msacsr) | c));
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}
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}
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@ -3059,9 +3065,11 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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switch (df) {
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switch (df) {
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case DF_WORD:
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case DF_WORD:
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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/* Half precision floats come in two formats: standard
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/*
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IEEE and "ARM" format. The latter gains extra exponent
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* Half precision floats come in two formats: standard
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range by omitting the NaN/Inf encodings. */
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* IEEE and "ARM" format. The latter gains extra exponent
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* range by omitting the NaN/Inf encodings.
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*/
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flag ieee = 1;
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flag ieee = 1;
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MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
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MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
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@ -3617,9 +3625,11 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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switch (df) {
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switch (df) {
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case DF_WORD:
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case DF_WORD:
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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/* Half precision floats come in two formats: standard
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/*
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IEEE and "ARM" format. The latter gains extra exponent
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* Half precision floats come in two formats: standard
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range by omitting the NaN/Inf encodings. */
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* IEEE and "ARM" format. The latter gains extra exponent
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* range by omitting the NaN/Inf encodings.
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*/
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flag ieee = 1;
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flag ieee = 1;
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MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
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MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
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@ -3651,9 +3661,11 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
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switch (df) {
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switch (df) {
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case DF_WORD:
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case DF_WORD:
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
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/* Half precision floats come in two formats: standard
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/*
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IEEE and "ARM" format. The latter gains extra exponent
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* Half precision floats come in two formats: standard
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range by omitting the NaN/Inf encodings. */
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* IEEE and "ARM" format. The latter gains extra exponent
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* range by omitting the NaN/Inf encodings.
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*/
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flag ieee = 1;
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flag ieee = 1;
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MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
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MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
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