hw/timer: Adding watchdog for NPCM7XX Timer.
The watchdog is part of NPCM7XX's timer module. Its behavior is controlled by the WTCR register in the timer. When enabled, the watchdog issues an interrupt signal after a pre-set amount of cycles, and issues a reset signal shortly after that. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: deleted blank line at end of npcm_watchdog_timer-test.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>stable-6.0
Hao Wu
Peter Maydell
parent
2ac88848cb
commit
7d378ed6e3
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@ -755,6 +755,7 @@ L: qemu-arm@nongnu.org
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S: Supported
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F: hw/*/npcm7xx*
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F: include/hw/*/npcm7xx*
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F: tests/qtest/npcm7xx*
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F: pc-bios/npcm7xx_bootrom.bin
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F: roms/vbootrom
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@ -86,6 +86,9 @@ enum NPCM7xxInterrupt {
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NPCM7XX_TIMER12_IRQ,
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NPCM7XX_TIMER13_IRQ,
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NPCM7XX_TIMER14_IRQ,
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NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
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NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
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NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
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};
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/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
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@ -353,6 +356,15 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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qemu_irq irq = npcm7xx_irq(s, first_irq + j);
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sysbus_connect_irq(sbd, j, irq);
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}
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/* IRQ for watchdogs */
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sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
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npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
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/* GPIO that connects clk module with watchdog */
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qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
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NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
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qdev_get_gpio_in_named(DEVICE(&s->clk),
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NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
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}
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/* UART0..3 (16550 compatible) */
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@ -17,6 +17,7 @@
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#include "qemu/osdep.h"
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#include "hw/misc/npcm7xx_clk.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "migration/vmstate.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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@ -24,6 +25,7 @@
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#include "qemu/timer.h"
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#include "qemu/units.h"
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#include "trace.h"
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#include "sysemu/watchdog.h"
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#define PLLCON_LOKI BIT(31)
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#define PLLCON_LOKS BIT(30)
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@ -87,6 +89,12 @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
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[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
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};
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/* Register Field Definitions */
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#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
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/* The number of watchdogs that can trigger a reset. */
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#define NPCM7XX_NR_WATCHDOGS (3)
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static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t reg = offset / sizeof(uint32_t);
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@ -187,6 +195,24 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
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s->regs[reg] = value;
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}
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/* Perform reset action triggered by a watchdog */
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static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
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int level)
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{
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NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);
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uint32_t rcr;
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g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
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rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n];
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if (rcr & NPCM7XX_CLK_WDRCR_CA9C) {
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watchdog_perform_action();
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} else {
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qemu_log_mask(LOG_UNIMP,
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"%s: only CPU reset is implemented. (requested 0x%" PRIx32")\n",
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__func__, rcr);
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}
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}
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static const struct MemoryRegionOps npcm7xx_clk_ops = {
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.read = npcm7xx_clk_read,
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.write = npcm7xx_clk_write,
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@ -226,6 +252,8 @@ static void npcm7xx_clk_init(Object *obj)
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memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
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TYPE_NPCM7XX_CLK, 4 * KiB);
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sysbus_init_mmio(&s->parent, &s->iomem);
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qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
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NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
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}
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static const VMStateDescription vmstate_npcm7xx_clk = {
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@ -17,6 +17,7 @@
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/npcm7xx_clk.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "migration/vmstate.h"
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@ -60,6 +61,50 @@ enum NPCM7xxTimerRegisters {
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#define NPCM7XX_TCSR_PRESCALE_START 0
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#define NPCM7XX_TCSR_PRESCALE_LEN 8
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#define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
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#define NPCM7XX_WTCR_FREEZE_EN BIT(9)
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#define NPCM7XX_WTCR_WTE BIT(7)
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#define NPCM7XX_WTCR_WTIE BIT(6)
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#define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
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#define NPCM7XX_WTCR_WTIF BIT(3)
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#define NPCM7XX_WTCR_WTRF BIT(2)
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#define NPCM7XX_WTCR_WTRE BIT(1)
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#define NPCM7XX_WTCR_WTR BIT(0)
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/*
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* The number of clock cycles between interrupt and reset in watchdog, used
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* by the software to handle the interrupt before system is reset.
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*/
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#define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
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/* Start or resume the timer. */
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static void npcm7xx_timer_start(NPCM7xxBaseTimer *t)
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{
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int64_t now;
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->expires_ns = now + t->remaining_ns;
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timer_mod(&t->qtimer, t->expires_ns);
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}
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/* Stop counting. Record the time remaining so we can continue later. */
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static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t)
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{
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int64_t now;
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timer_del(&t->qtimer);
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->remaining_ns = t->expires_ns - now;
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}
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/* Delete the timer and reset it to default state. */
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static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t)
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{
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timer_del(&t->qtimer);
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t->expires_ns = 0;
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t->remaining_ns = 0;
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}
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/*
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* Returns the index of timer in the tc->timer array. This can be used to
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* locate the registers that belong to this timer.
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@ -102,6 +147,52 @@ static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
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return count;
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}
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static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
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{
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switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) {
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case 0:
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return 1;
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case 1:
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return 256;
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case 2:
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return 2048;
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case 3:
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return 65536;
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default:
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g_assert_not_reached();
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}
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}
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static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
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int64_t cycles)
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{
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uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
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int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
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/*
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* The reset function always clears the current timer. The caller of the
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* this needs to decide whether to start the watchdog timer based on
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* specific flag in WTCR.
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*/
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npcm7xx_timer_clear(&t->base_timer);
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ns *= prescaler;
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t->base_timer.remaining_ns = ns;
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}
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static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t)
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{
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int64_t cycles = 1;
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uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr);
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g_assert(s <= 3);
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cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT;
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cycles <<= 2 * s;
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npcm7xx_watchdog_timer_reset_cycles(t, cycles);
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}
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/*
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* Raise the interrupt line if there's a pending interrupt and interrupts are
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* enabled for this timer. If not, lower it.
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@ -116,16 +207,6 @@ static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
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trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
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}
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/* Start or resume the timer. */
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static void npcm7xx_timer_start(NPCM7xxTimer *t)
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{
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int64_t now;
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->expires_ns = now + t->remaining_ns;
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timer_mod(&t->qtimer, t->expires_ns);
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}
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/*
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* Called when the counter reaches zero. Sets the interrupt flag, and either
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* restarts or disables the timer.
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@ -138,9 +219,9 @@ static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
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tc->tisr |= BIT(index);
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if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
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t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_start(t);
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npcm7xx_timer_start(&t->base_timer);
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}
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} else {
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t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
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@ -149,15 +230,6 @@ static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
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npcm7xx_timer_check_interrupt(t);
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}
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/* Stop counting. Record the time remaining so we can continue later. */
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static void npcm7xx_timer_pause(NPCM7xxTimer *t)
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{
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int64_t now;
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timer_del(&t->qtimer);
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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t->remaining_ns = t->expires_ns - now;
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}
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/*
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* Restart the timer from its initial value. If the timer was enabled and stays
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@ -167,10 +239,10 @@ static void npcm7xx_timer_pause(NPCM7xxTimer *t)
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*/
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static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
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{
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t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
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if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_start(t);
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npcm7xx_timer_start(&t->base_timer);
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}
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}
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@ -181,10 +253,10 @@ static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
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if (t->tcsr & NPCM7XX_TCSR_CEN) {
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
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return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now);
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}
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return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
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return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns);
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}
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static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
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@ -216,9 +288,9 @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
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if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
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/* Recalculate time remaining based on the current TDR value. */
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t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
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t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
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if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
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npcm7xx_timer_start(t);
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npcm7xx_timer_start(&t->base_timer);
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}
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}
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@ -232,11 +304,11 @@ static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
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if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
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if (new_tcsr & NPCM7XX_TCSR_CEN) {
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t->tcsr |= NPCM7XX_TCSR_CACT;
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npcm7xx_timer_start(t);
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npcm7xx_timer_start(&t->base_timer);
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} else {
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t->tcsr &= ~NPCM7XX_TCSR_CACT;
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npcm7xx_timer_pause(t);
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if (t->remaining_ns <= 0) {
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npcm7xx_timer_pause(&t->base_timer);
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if (t->base_timer.remaining_ns <= 0) {
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npcm7xx_timer_reached_zero(t);
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}
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}
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@ -259,9 +331,47 @@ static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
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if (value & (1U << i)) {
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npcm7xx_timer_check_interrupt(&s->timer[i]);
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}
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}
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}
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static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr)
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{
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uint32_t old_wtcr = t->wtcr;
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/*
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* WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
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* unchanged.
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*/
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if (new_wtcr & NPCM7XX_WTCR_WTIF) {
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new_wtcr &= ~NPCM7XX_WTCR_WTIF;
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} else if (old_wtcr & NPCM7XX_WTCR_WTIF) {
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new_wtcr |= NPCM7XX_WTCR_WTIF;
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}
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if (new_wtcr & NPCM7XX_WTCR_WTRF) {
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new_wtcr &= ~NPCM7XX_WTCR_WTRF;
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} else if (old_wtcr & NPCM7XX_WTCR_WTRF) {
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new_wtcr |= NPCM7XX_WTCR_WTRF;
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}
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t->wtcr = new_wtcr;
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if (new_wtcr & NPCM7XX_WTCR_WTR) {
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t->wtcr &= ~NPCM7XX_WTCR_WTR;
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npcm7xx_watchdog_timer_reset(t);
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if (new_wtcr & NPCM7XX_WTCR_WTE) {
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npcm7xx_timer_start(&t->base_timer);
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}
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} else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) {
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if (new_wtcr & NPCM7XX_WTCR_WTE) {
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npcm7xx_timer_start(&t->base_timer);
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} else {
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npcm7xx_timer_pause(&t->base_timer);
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}
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}
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}
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static hwaddr npcm7xx_tcsr_index(hwaddr reg)
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{
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switch (reg) {
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@ -353,7 +463,7 @@ static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
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break;
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case NPCM7XX_TIMER_WTCR:
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value = s->wtcr;
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value = s->watchdog_timer.wtcr;
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break;
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default:
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@ -409,8 +519,7 @@ static void npcm7xx_timer_write(void *opaque, hwaddr offset,
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return;
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case NPCM7XX_TIMER_WTCR:
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qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
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__func__, value);
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npcm7xx_timer_write_wtcr(&s->watchdog_timer, value);
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return;
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}
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@ -448,15 +557,42 @@ static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
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for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
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NPCM7xxTimer *t = &s->timer[i];
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timer_del(&t->qtimer);
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t->expires_ns = 0;
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t->remaining_ns = 0;
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npcm7xx_timer_clear(&t->base_timer);
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t->tcsr = 0x00000005;
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t->ticr = 0x00000000;
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}
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s->tisr = 0x00000000;
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||||
s->wtcr = 0x00000400;
|
||||
/*
|
||||
* Set WTCLK to 1(default) and reset all flags except WTRF.
|
||||
* WTRF is not reset during a core domain reset.
|
||||
*/
|
||||
s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr &
|
||||
NPCM7XX_WTCR_WTRF);
|
||||
}
|
||||
|
||||
static void npcm7xx_watchdog_timer_expired(void *opaque)
|
||||
{
|
||||
NPCM7xxWatchdogTimer *t = opaque;
|
||||
|
||||
if (t->wtcr & NPCM7XX_WTCR_WTE) {
|
||||
if (t->wtcr & NPCM7XX_WTCR_WTIF) {
|
||||
if (t->wtcr & NPCM7XX_WTCR_WTRE) {
|
||||
t->wtcr |= NPCM7XX_WTCR_WTRF;
|
||||
/* send reset signal to CLK module*/
|
||||
qemu_irq_raise(t->reset_signal);
|
||||
}
|
||||
} else {
|
||||
t->wtcr |= NPCM7XX_WTCR_WTIF;
|
||||
if (t->wtcr & NPCM7XX_WTCR_WTIE) {
|
||||
/* send interrupt */
|
||||
qemu_irq_raise(t->irq);
|
||||
}
|
||||
npcm7xx_watchdog_timer_reset_cycles(t,
|
||||
NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES);
|
||||
npcm7xx_timer_start(&t->base_timer);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void npcm7xx_timer_hold_reset(Object *obj)
|
||||
|
|
@ -467,6 +603,7 @@ static void npcm7xx_timer_hold_reset(Object *obj)
|
|||
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
||||
qemu_irq_lower(s->timer[i].irq);
|
||||
}
|
||||
qemu_irq_lower(s->watchdog_timer.irq);
|
||||
}
|
||||
|
||||
static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
|
||||
|
|
@ -474,43 +611,80 @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
|
|||
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
|
||||
SysBusDevice *sbd = &s->parent;
|
||||
int i;
|
||||
NPCM7xxWatchdogTimer *w;
|
||||
|
||||
for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
|
||||
NPCM7xxTimer *t = &s->timer[i];
|
||||
t->ctrl = s;
|
||||
timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
|
||||
timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
|
||||
npcm7xx_timer_expired, t);
|
||||
sysbus_init_irq(sbd, &t->irq);
|
||||
}
|
||||
|
||||
w = &s->watchdog_timer;
|
||||
w->ctrl = s;
|
||||
timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL,
|
||||
npcm7xx_watchdog_timer_expired, w);
|
||||
sysbus_init_irq(sbd, &w->irq);
|
||||
|
||||
memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
|
||||
TYPE_NPCM7XX_TIMER, 4 * KiB);
|
||||
sysbus_init_mmio(sbd, &s->iomem);
|
||||
qdev_init_gpio_out_named(dev, &w->reset_signal,
|
||||
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_npcm7xx_timer = {
|
||||
.name = "npcm7xx-timer",
|
||||
static const VMStateDescription vmstate_npcm7xx_base_timer = {
|
||||
.name = "npcm7xx-base-timer",
|
||||
.version_id = 0,
|
||||
.minimum_version_id = 0,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_TIMER(qtimer, NPCM7xxTimer),
|
||||
VMSTATE_INT64(expires_ns, NPCM7xxTimer),
|
||||
VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
|
||||
VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer),
|
||||
VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer),
|
||||
VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_npcm7xx_timer = {
|
||||
.name = "npcm7xx-timer",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_STRUCT(base_timer, NPCM7xxTimer,
|
||||
0, vmstate_npcm7xx_base_timer,
|
||||
NPCM7xxBaseTimer),
|
||||
VMSTATE_UINT32(tcsr, NPCM7xxTimer),
|
||||
VMSTATE_UINT32(ticr, NPCM7xxTimer),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
|
||||
.name = "npcm7xx-timer-ctrl",
|
||||
static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
|
||||
.name = "npcm7xx-watchdog-timer",
|
||||
.version_id = 0,
|
||||
.minimum_version_id = 0,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer,
|
||||
0, vmstate_npcm7xx_base_timer,
|
||||
NPCM7xxBaseTimer),
|
||||
VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
|
||||
.name = "npcm7xx-timer-ctrl",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
|
||||
VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
|
||||
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
|
||||
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
|
||||
NPCM7xxTimer),
|
||||
VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState,
|
||||
0, vmstate_npcm7xx_watchdog_timer,
|
||||
NPCM7xxWatchdogTimer),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@
|
|||
*/
|
||||
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
|
||||
|
||||
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
|
||||
|
||||
typedef struct NPCM7xxCLKState {
|
||||
SysBusDevice parent;
|
||||
|
||||
|
|
|
|||
|
|
@ -29,14 +29,31 @@
|
|||
*/
|
||||
#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
|
||||
|
||||
/* The basic watchdog timer period is 2^14 clock cycles. */
|
||||
#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
|
||||
|
||||
#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
|
||||
|
||||
typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
|
||||
|
||||
/**
|
||||
* struct NPCM7xxTimer - Individual timer state.
|
||||
* @irq: GIC interrupt line to fire on expiration (if enabled).
|
||||
* struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
|
||||
* watchdog timer use.
|
||||
* @qtimer: QEMU timer that notifies us on expiration.
|
||||
* @expires_ns: Absolute virtual expiration time.
|
||||
* @remaining_ns: Remaining time until expiration if timer is paused.
|
||||
*/
|
||||
typedef struct NPCM7xxBaseTimer {
|
||||
QEMUTimer qtimer;
|
||||
int64_t expires_ns;
|
||||
int64_t remaining_ns;
|
||||
} NPCM7xxBaseTimer;
|
||||
|
||||
/**
|
||||
* struct NPCM7xxTimer - Individual timer state.
|
||||
* @ctrl: The timer module that owns this timer.
|
||||
* @irq: GIC interrupt line to fire on expiration (if enabled).
|
||||
* @base_timer: The basic timer functionality for this timer.
|
||||
* @tcsr: The Timer Control and Status Register.
|
||||
* @ticr: The Timer Initial Count Register.
|
||||
*/
|
||||
|
|
@ -44,21 +61,38 @@ typedef struct NPCM7xxTimer {
|
|||
NPCM7xxTimerCtrlState *ctrl;
|
||||
|
||||
qemu_irq irq;
|
||||
QEMUTimer qtimer;
|
||||
int64_t expires_ns;
|
||||
int64_t remaining_ns;
|
||||
NPCM7xxBaseTimer base_timer;
|
||||
|
||||
uint32_t tcsr;
|
||||
uint32_t ticr;
|
||||
} NPCM7xxTimer;
|
||||
|
||||
/**
|
||||
* struct NPCM7xxWatchdogTimer - The watchdog timer state.
|
||||
* @ctrl: The timer module that owns this timer.
|
||||
* @irq: GIC interrupt line to fire on expiration (if enabled).
|
||||
* @reset_signal: The GPIO used to send a reset signal.
|
||||
* @base_timer: The basic timer functionality for this timer.
|
||||
* @wtcr: The Watchdog Timer Control Register.
|
||||
*/
|
||||
typedef struct NPCM7xxWatchdogTimer {
|
||||
NPCM7xxTimerCtrlState *ctrl;
|
||||
|
||||
qemu_irq irq;
|
||||
qemu_irq reset_signal;
|
||||
NPCM7xxBaseTimer base_timer;
|
||||
|
||||
uint32_t wtcr;
|
||||
} NPCM7xxWatchdogTimer;
|
||||
|
||||
/**
|
||||
* struct NPCM7xxTimerCtrlState - Timer Module device state.
|
||||
* @parent: System bus device.
|
||||
* @iomem: Memory region through which registers are accessed.
|
||||
* @index: The index of this timer module.
|
||||
* @tisr: The Timer Interrupt Status Register.
|
||||
* @wtcr: The Watchdog Timer Control Register.
|
||||
* @timer: The five individual timers managed by this module.
|
||||
* @watchdog_timer: The watchdog timer managed by this module.
|
||||
*/
|
||||
struct NPCM7xxTimerCtrlState {
|
||||
SysBusDevice parent;
|
||||
|
|
@ -66,9 +100,9 @@ struct NPCM7xxTimerCtrlState {
|
|||
MemoryRegion iomem;
|
||||
|
||||
uint32_t tisr;
|
||||
uint32_t wtcr;
|
||||
|
||||
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
|
||||
NPCM7xxWatchdogTimer watchdog_timer;
|
||||
};
|
||||
|
||||
#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ qtests_sparc64 = \
|
|||
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
|
||||
['prom-env-test', 'boot-serial-test']
|
||||
|
||||
qtests_npcm7xx = ['npcm7xx_timer-test']
|
||||
qtests_npcm7xx = ['npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test']
|
||||
qtests_arm = \
|
||||
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
|
||||
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,319 @@
|
|||
/*
|
||||
* QTests for Nuvoton NPCM7xx Timer Watchdog Modules.
|
||||
*
|
||||
* Copyright 2020 Google LLC
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/timer.h"
|
||||
|
||||
#include "libqos/libqtest.h"
|
||||
#include "qapi/qmp/qdict.h"
|
||||
|
||||
#define WTCR_OFFSET 0x1c
|
||||
#define REF_HZ (25000000)
|
||||
|
||||
/* WTCR bit fields */
|
||||
#define WTCLK(rv) ((rv) << 10)
|
||||
#define WTE BIT(7)
|
||||
#define WTIE BIT(6)
|
||||
#define WTIS(rv) ((rv) << 4)
|
||||
#define WTIF BIT(3)
|
||||
#define WTRF BIT(2)
|
||||
#define WTRE BIT(1)
|
||||
#define WTR BIT(0)
|
||||
|
||||
typedef struct Watchdog {
|
||||
int irq;
|
||||
uint64_t base_addr;
|
||||
} Watchdog;
|
||||
|
||||
static const Watchdog watchdog_list[] = {
|
||||
{
|
||||
.irq = 47,
|
||||
.base_addr = 0xf0008000
|
||||
},
|
||||
{
|
||||
.irq = 48,
|
||||
.base_addr = 0xf0009000
|
||||
},
|
||||
{
|
||||
.irq = 49,
|
||||
.base_addr = 0xf000a000
|
||||
}
|
||||
};
|
||||
|
||||
static int watchdog_index(const Watchdog *wd)
|
||||
{
|
||||
ptrdiff_t diff = wd - watchdog_list;
|
||||
|
||||
g_assert(diff >= 0 && diff < ARRAY_SIZE(watchdog_list));
|
||||
|
||||
return diff;
|
||||
}
|
||||
|
||||
static uint32_t watchdog_read_wtcr(QTestState *qts, const Watchdog *wd)
|
||||
{
|
||||
return qtest_readl(qts, wd->base_addr + WTCR_OFFSET);
|
||||
}
|
||||
|
||||
static void watchdog_write_wtcr(QTestState *qts, const Watchdog *wd,
|
||||
uint32_t value)
|
||||
{
|
||||
qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value);
|
||||
}
|
||||
|
||||
static uint32_t watchdog_prescaler(QTestState *qts, const Watchdog *wd)
|
||||
{
|
||||
switch (extract32(watchdog_read_wtcr(qts, wd), 10, 2)) {
|
||||
case 0:
|
||||
return 1;
|
||||
case 1:
|
||||
return 256;
|
||||
case 2:
|
||||
return 2048;
|
||||
case 3:
|
||||
return 65536;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
}
|
||||
|
||||
static QDict *get_watchdog_action(QTestState *qts)
|
||||
{
|
||||
QDict *ev = qtest_qmp_eventwait_ref(qts, "WATCHDOG");
|
||||
QDict *data;
|
||||
|
||||
data = qdict_get_qdict(ev, "data");
|
||||
qobject_ref(data);
|
||||
qobject_unref(ev);
|
||||
return data;
|
||||
}
|
||||
|
||||
#define RESET_CYCLES 1024
|
||||
static uint32_t watchdog_interrupt_cycles(QTestState *qts, const Watchdog *wd)
|
||||
{
|
||||
uint32_t wtis = extract32(watchdog_read_wtcr(qts, wd), 4, 2);
|
||||
return 1 << (14 + 2 * wtis);
|
||||
}
|
||||
|
||||
static int64_t watchdog_calculate_steps(uint32_t count, uint32_t prescale)
|
||||
{
|
||||
return (NANOSECONDS_PER_SECOND / REF_HZ) * count * prescale;
|
||||
}
|
||||
|
||||
static int64_t watchdog_interrupt_steps(QTestState *qts, const Watchdog *wd)
|
||||
{
|
||||
return watchdog_calculate_steps(watchdog_interrupt_cycles(qts, wd),
|
||||
watchdog_prescaler(qts, wd));
|
||||
}
|
||||
|
||||
/* Check wtcr can be reset to default value */
|
||||
static void test_init(gconstpointer watchdog)
|
||||
{
|
||||
const Watchdog *wd = watchdog;
|
||||
QTestState *qts = qtest_init("-machine quanta-gsj");
|
||||
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(1) | WTRF | WTIF | WTR);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
/* Check a watchdog can generate interrupt and reset actions */
|
||||
static void test_reset_action(gconstpointer watchdog)
|
||||
{
|
||||
const Watchdog *wd = watchdog;
|
||||
QTestState *qts = qtest_init("-machine quanta-gsj");
|
||||
QDict *ad;
|
||||
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
|
||||
watchdog_write_wtcr(qts, wd,
|
||||
WTCLK(0) | WTE | WTRF | WTRE | WTIF | WTIE | WTR);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
|
||||
WTCLK(0) | WTE | WTRE | WTIE);
|
||||
|
||||
/* Check a watchdog can generate an interrupt */
|
||||
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
|
||||
WTCLK(0) | WTE | WTIF | WTIE | WTRE);
|
||||
g_assert_true(qtest_get_irq(qts, wd->irq));
|
||||
|
||||
/* Check a watchdog can generate a reset signal */
|
||||
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
|
||||
watchdog_prescaler(qts, wd)));
|
||||
ad = get_watchdog_action(qts);
|
||||
/* The signal is a reset signal */
|
||||
g_assert_false(strcmp(qdict_get_str(ad, "action"), "reset"));
|
||||
qobject_unref(ad);
|
||||
qtest_qmp_eventwait(qts, "RESET");
|
||||
/*
|
||||
* Make sure WTCR is reset to default except for WTRF bit which shouldn't
|
||||
* be reset.
|
||||
*/
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(1) | WTRF);
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
/* Check a watchdog works with all possible WTCLK prescalers and WTIS cycles */
|
||||
static void test_prescaler(gconstpointer watchdog)
|
||||
{
|
||||
const Watchdog *wd = watchdog;
|
||||
|
||||
for (int wtclk = 0; wtclk < 4; ++wtclk) {
|
||||
for (int wtis = 0; wtis < 4; ++wtis) {
|
||||
QTestState *qts = qtest_init("-machine quanta-gsj");
|
||||
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
watchdog_write_wtcr(qts, wd,
|
||||
WTCLK(wtclk) | WTE | WTIF | WTIS(wtis) | WTIE | WTR);
|
||||
/*
|
||||
* The interrupt doesn't fire until watchdog_interrupt_steps()
|
||||
* cycles passed
|
||||
*/
|
||||
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd) - 1);
|
||||
g_assert_false(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_false(qtest_get_irq(qts, wd->irq));
|
||||
qtest_clock_step(qts, 1);
|
||||
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_true(qtest_get_irq(qts, wd->irq));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Check a watchdog doesn't fire if corresponding flags (WTIE and WTRE) are not
|
||||
* set.
|
||||
*/
|
||||
static void test_enabling_flags(gconstpointer watchdog)
|
||||
{
|
||||
const Watchdog *wd = watchdog;
|
||||
QTestState *qts;
|
||||
|
||||
/* Neither WTIE or WTRE is set, no interrupt or reset should happen */
|
||||
qts = qtest_init("-machine quanta-gsj");
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRF | WTR);
|
||||
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
|
||||
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_false(qtest_get_irq(qts, wd->irq));
|
||||
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
|
||||
watchdog_prescaler(qts, wd)));
|
||||
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
|
||||
qtest_quit(qts);
|
||||
|
||||
/* Only WTIE is set, interrupt is triggered but reset should not happen */
|
||||
qts = qtest_init("-machine quanta-gsj");
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
|
||||
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
|
||||
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_true(qtest_get_irq(qts, wd->irq));
|
||||
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
|
||||
watchdog_prescaler(qts, wd)));
|
||||
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_false(watchdog_read_wtcr(qts, wd) & WTRF);
|
||||
qtest_quit(qts);
|
||||
|
||||
/* Only WTRE is set, interrupt is triggered but reset should not happen */
|
||||
qts = qtest_init("-machine quanta-gsj");
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTRE | WTRF | WTR);
|
||||
qtest_clock_step(qts, watchdog_interrupt_steps(qts, wd));
|
||||
g_assert_true(watchdog_read_wtcr(qts, wd) & WTIF);
|
||||
g_assert_false(qtest_get_irq(qts, wd->irq));
|
||||
qtest_clock_step(qts, watchdog_calculate_steps(RESET_CYCLES,
|
||||
watchdog_prescaler(qts, wd)));
|
||||
g_assert_false(strcmp(qdict_get_str(get_watchdog_action(qts), "action"),
|
||||
"reset"));
|
||||
qtest_qmp_eventwait(qts, "RESET");
|
||||
qtest_quit(qts);
|
||||
|
||||
/*
|
||||
* The case when both flags are set is already tested in
|
||||
* test_reset_action().
|
||||
*/
|
||||
}
|
||||
|
||||
/* Check a watchdog can pause and resume by setting WTE bits */
|
||||
static void test_pause(gconstpointer watchdog)
|
||||
{
|
||||
const Watchdog *wd = watchdog;
|
||||
QTestState *qts;
|
||||
int64_t remaining_steps, steps;
|
||||
|
||||
qts = qtest_init("-machine quanta-gsj");
|
||||
qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIF | WTIE | WTRF | WTR);
|
||||
remaining_steps = watchdog_interrupt_steps(qts, wd);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
|
||||
|
||||
/* Run for half of the execution period. */
|
||||
steps = remaining_steps / 2;
|
||||
remaining_steps -= steps;
|
||||
qtest_clock_step(qts, steps);
|
||||
|
||||
/* Pause the watchdog */
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTIE);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
|
||||
|
||||
/* Run for a long period of time, the watchdog shouldn't fire */
|
||||
qtest_clock_step(qts, steps << 4);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTIE);
|
||||
g_assert_false(qtest_get_irq(qts, wd->irq));
|
||||
|
||||
/* Resume the watchdog */
|
||||
watchdog_write_wtcr(qts, wd, WTCLK(0) | WTE | WTIE);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==, WTCLK(0) | WTE | WTIE);
|
||||
|
||||
/* Run for the reset of the execution period, the watchdog should fire */
|
||||
qtest_clock_step(qts, remaining_steps);
|
||||
g_assert_cmphex(watchdog_read_wtcr(qts, wd), ==,
|
||||
WTCLK(0) | WTE | WTIF | WTIE);
|
||||
g_assert_true(qtest_get_irq(qts, wd->irq));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
static void watchdog_add_test(const char *name, const Watchdog* wd,
|
||||
GTestDataFunc fn)
|
||||
{
|
||||
g_autofree char *full_name = g_strdup_printf(
|
||||
"npcm7xx_watchdog_timer[%d]/%s", watchdog_index(wd), name);
|
||||
qtest_add_data_func(full_name, wd, fn);
|
||||
}
|
||||
#define add_test(name, td) watchdog_add_test(#name, td, test_##name)
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
g_test_set_nonfatal_assertions();
|
||||
|
||||
for (int i = 0; i < ARRAY_SIZE(watchdog_list); ++i) {
|
||||
const Watchdog *wd = &watchdog_list[i];
|
||||
|
||||
add_test(init, wd);
|
||||
add_test(reset_action, wd);
|
||||
add_test(prescaler, wd);
|
||||
add_test(enabling_flags, wd);
|
||||
add_test(pause, wd);
|
||||
}
|
||||
|
||||
return g_test_run();
|
||||
}
|
||||
Loading…
Reference in New Issue