target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
We cannot easily create "any" functions for these, because the ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. Which means that an aarch32-only cpu will return incorrect results when testing the aarch64 registers. To use these, we must either have context or additionally test vs ARM_FEATURE_AARCH64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj)
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* KVM does not currently allow us to lie to the guest about its
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* ID/feature registers, so the guest always sees what the host has.
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*/
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if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
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if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
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? cpu_isar_feature(aa64_fp_simd, cpu)
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: cpu_isar_feature(aa32_vfp, cpu)) {
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cpu->has_vfp = true;
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if (!kvm_enabled()) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
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@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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* We rely on no XScale CPU having VFP so we can use the same bits in the
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* TB flags field for VECSTRIDE and XSCALE_CPAR.
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*/
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assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
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arm_feature(env, ARM_FEATURE_XSCALE)));
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assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
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!cpu_isar_feature(aa32_vfp_simd, cpu) ||
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!arm_feature(env, ARM_FEATURE_XSCALE));
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if (arm_feature(env, ARM_FEATURE_V7) &&
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!arm_feature(env, ARM_FEATURE_M) &&
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@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
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return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
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}
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static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
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{
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return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
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}
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/*
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* We always set the FP and SIMD FP16 fields to indicate identical
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* levels of support (assuming SIMD is implemented at all), so
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@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
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}
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static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
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{
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/* We always set the AdvSIMD and FP fields identically. */
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
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}
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static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
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{
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/* We always set the AdvSIMD and FP fields identically wrt FP16. */
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@ -9,9 +9,10 @@
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static bool vfp_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_VFP);
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return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
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? cpu_isar_feature(aa64_fp_simd, cpu)
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: cpu_isar_feature(aa32_vfp_simd, cpu));
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}
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static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
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