Merge remote branch 'mst/pci' into staging
This commit is contained in:
commit
7d834c7450
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@ -48,15 +48,6 @@
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#include "net.h"
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#include "net.h"
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#include "eeprom93xx.h"
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#include "eeprom93xx.h"
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/* Common declarations for all PCI devices. */
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#define PCI_CONFIG_8(offset, value) \
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(pci_conf[offset] = (value))
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#define PCI_CONFIG_16(offset, value) \
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(*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
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#define PCI_CONFIG_32(offset, value) \
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(*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
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#define KiB 1024
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#define KiB 1024
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/* Debug EEPRO100 card. */
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/* Debug EEPRO100 card. */
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@ -467,49 +458,28 @@ static void pci_reset(EEPRO100State * s)
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/* PCI Vendor ID */
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/* PCI Vendor ID */
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
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/* PCI Device ID depends on device and is set below. */
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/* PCI Device ID depends on device and is set below. */
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/* PCI Command */
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/* TODO: this is the default, do not override. */
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PCI_CONFIG_16(PCI_COMMAND, 0x0000);
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/* PCI Status */
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/* PCI Status */
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/* TODO: Value at RST# should be 0. */
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
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/* PCI Revision ID */
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/* PCI Revision ID */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
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/* TODO: this is the default, do not override. */
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/* PCI Class Code */
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PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
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pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
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pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
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/* PCI Cache Line Size */
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/* check cache line size!!! */
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#if 0
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PCI_CONFIG_8(0x0c, 0x00);
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#endif
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/* PCI Latency Timer */
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/* PCI Latency Timer */
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PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
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pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
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/* PCI Header Type */
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/* BIST (built-in self test) */
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/* Expansion ROM Base Address (depends on boot disable!!!) */
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/* TODO: not needed, set when BAR is registered */
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PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
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/* Capability Pointer */
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/* Capability Pointer */
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/* TODO: revisions with power_management 1 use this but
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/* TODO: revisions with power_management 1 use this but
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* do not set new capability list bit in status register. */
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* do not set new capability list bit in status register. */
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PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
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pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0xdc);
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/* Interrupt Line */
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/* Interrupt Pin */
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/* TODO: RST# value should be 0 */
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PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); /* interrupt pin 0 */
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/* Minimum Grant */
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/* Minimum Grant */
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PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
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pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
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/* Maximum Latency */
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/* Maximum Latency */
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PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
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pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
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switch (device) {
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switch (device) {
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case i82550:
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case i82550:
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/* TODO: check device id. */
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/* TODO: check device id. */
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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/* Revision ID: 0x0c, 0x0d, 0x0e. */
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/* Revision ID: 0x0c, 0x0d, 0x0e. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
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/* TODO: check size of statistical counters. */
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/* TODO: check size of statistical counters. */
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s->stats_size = 80;
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s->stats_size = 80;
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/* TODO: check extended tcb support. */
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/* TODO: check extended tcb support. */
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@ -518,80 +488,80 @@ static void pci_reset(EEPRO100State * s)
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case i82551:
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case i82551:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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/* Revision ID: 0x0f, 0x10. */
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/* Revision ID: 0x0f, 0x10. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0f);
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/* TODO: check size of statistical counters. */
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/* TODO: check size of statistical counters. */
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s->stats_size = 80;
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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case i82557A:
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case i82557A:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x01);
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PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
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pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
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power_management = 0;
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power_management = 0;
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break;
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break;
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case i82557B:
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case i82557B:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x02);
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PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
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pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
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power_management = 0;
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power_management = 0;
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break;
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break;
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case i82557C:
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case i82557C:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x03);
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PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
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pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
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power_management = 0;
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power_management = 0;
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break;
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break;
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case i82558A:
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case i82558A:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x04);
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s->stats_size = 76;
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s->stats_size = 76;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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case i82558B:
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case i82558B:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x05);
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s->stats_size = 76;
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s->stats_size = 76;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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case i82559A:
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case i82559A:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x06);
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s->stats_size = 80;
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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case i82559B:
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case i82559B:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x07);
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s->stats_size = 80;
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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case i82559C:
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case i82559C:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
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/* TODO: Windows wants revision id 0x0c. */
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/* TODO: Windows wants revision id 0x0c. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0c);
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#if EEPROM_SIZE > 0
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#if EEPROM_SIZE > 0
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PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
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pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
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PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
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pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
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#endif
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#endif
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s->stats_size = 80;
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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case i82559ER:
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case i82559ER:
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
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PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x09);
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s->stats_size = 80;
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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@ -599,7 +569,7 @@ static void pci_reset(EEPRO100State * s)
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/* TODO: check device id. */
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/* TODO: check device id. */
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
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/* TODO: wrong revision id. */
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/* TODO: wrong revision id. */
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PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
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pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
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s->stats_size = 80;
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s->stats_size = 80;
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s->has_extended_tcb_support = 1;
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s->has_extended_tcb_support = 1;
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break;
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break;
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@ -633,10 +603,10 @@ static void pci_reset(EEPRO100State * s)
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if (power_management) {
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if (power_management) {
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/* Power Management Capabilities */
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/* Power Management Capabilities */
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PCI_CONFIG_8(0xdc, 0x01);
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pci_set_byte(pci_conf + 0xdc, 0x01);
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/* Next Item Pointer */
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/* Next Item Pointer */
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/* Capability ID */
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/* Capability ID */
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PCI_CONFIG_16(0xde, 0x7e21);
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pci_set_word(pci_conf + 0xde, 0x7e21);
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/* TODO: Power Management Control / Status. */
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/* TODO: Power Management Control / Status. */
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/* TODO: Ethernet Power Consumption Registers (i82559 and later). */
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/* TODO: Ethernet Power Consumption Registers (i82559 and later). */
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}
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}
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@ -1997,6 +1997,9 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_0 + 4,
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_0 + 4,
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PCI_BASE_ADDRESS_SPACE_MEMORY);
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PCI_BASE_ADDRESS_SPACE_MEMORY);
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pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
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pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
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/* TODO: value must be 0 at RST# */
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/* TODO: value must be 0 at RST# */
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pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
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pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
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pci_conf[PCI_MIN_GNT] = 0x06;
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pci_conf[PCI_MIN_GNT] = 0x06;
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