TriCore RR, RR1 insn added and several bug fixes
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCgAGBQJUlxPPAAoJEArSxjlracoUUlsP/0o7MEiS7cDLw/7akoMWt3rc NqHbrAkPBhgF7OhTOtrd62nN8opw3ZxAPvctlJakVOLJ5dL+b+oEvFmULY1VpEx0 AzHaCN2oB1u4ZhvukQiwr/MuwZN1nk0EFvBFhnDGvhoHgHTAkxAaq1/7bZaJBUpO YBsNFSRF4CDibDb1v1x8JZNx4Cie9RpftObBnJJG0qDffx/u9OEpp0HvyDdJfPfQ crYOy/Omy0wfjZrEJnMeu7lz+KDXLmeJ+Xqj/Id5IC9rcVbua+Q1Sa4FfTdem+3a hiyQPyQXJvzGmme8kY9tGJtpQv7AyW0+PoOQO0pUcgyyXGod9rurNtbN29IGyWkf AkzVJ40XyG0gCkUsuzVaJeplORAFLiCVLhU3Bm458tOz9j9NPH8phQ1THBfunhqR S2uBmFbkgWUAOTebIiXXnFdLGoD4iMivH6og/MpZLzf9M0ThHqDLrHPt76cNLwYL 9kgv0dPpazXx+OCsRs1ss3WoYAWJg0eSB5gBSUaU26Xd6p2T/Bno0WAR7aOqIrkY fkNh+CXioG4U0x1jzp81ws0wqsxvVrAGRY74W17jH3y/JLQICiz40j3bVcIAxUMs TcfooHo4gcSbY2ZedlJCRGsMtKwXplosEXCrdkKA6SgltqCbUgsvliDUxYvHyj7t 6U4k1sy4qRy5mFxnP21W =7DhE -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20141221' into staging TriCore RR, RR1 insn added and several bug fixes # gpg: Signature made Sun 21 Dec 2014 18:39:11 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20141221: target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode target-tricore: Fix MFCR/MTCR insn and B format offset. target-tricore: Add missing 1.6 insn of BOL opcode format target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 target-tricore: Fix mask handling JNZ.T being 7 bit long target-tricore: pretty-print register dump and show more status registers target-tricore: add missing 64-bit MOV in RLC format target-tricore: typo in BOL format target-tricore: fix offset masking in BOL format Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
7db96d6cf8
|
|
@ -18,8 +18,12 @@
|
|||
/* Arithmetic */
|
||||
DEF_HELPER_3(add_ssov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(add_suov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(add_h_ssov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(add_h_suov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_suov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_h_ssov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_h_suov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(mul_ssov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(mul_suov, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sha_ssov, i32, env, i32, i32)
|
||||
|
|
@ -32,6 +36,61 @@ DEF_HELPER_4(msub32_ssov, i32, env, i32, i32, i32)
|
|||
DEF_HELPER_4(msub32_suov, i32, env, i32, i32, i32)
|
||||
DEF_HELPER_4(msub64_ssov, i64, env, i32, i64, i32)
|
||||
DEF_HELPER_4(msub64_suov, i64, env, i32, i64, i32)
|
||||
DEF_HELPER_3(absdif_h_ssov, i32, env, i32, i32)
|
||||
DEF_HELPER_2(abs_ssov, i32, env, i32)
|
||||
DEF_HELPER_2(abs_h_ssov, i32, env, i32)
|
||||
/* hword/byte arithmetic */
|
||||
DEF_HELPER_2(abs_b, i32, env, i32)
|
||||
DEF_HELPER_2(abs_h, i32, env, i32)
|
||||
DEF_HELPER_3(absdif_b, i32, env, i32, i32)
|
||||
DEF_HELPER_3(absdif_h, i32, env, i32, i32)
|
||||
DEF_HELPER_3(add_b, i32, env, i32, i32)
|
||||
DEF_HELPER_3(add_h, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_b, i32, env, i32, i32)
|
||||
DEF_HELPER_3(sub_h, i32, env, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(eq_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(eq_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(eqany_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(eqany_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(lt_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(lt_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(lt_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(lt_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(max_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(max_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(max_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(max_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(min_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(min_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(min_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(min_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
/* count leading ... */
|
||||
DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(clo_h, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(clz_h, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(cls, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(cls_h, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
/* sh */
|
||||
DEF_HELPER_FLAGS_2(sh, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_2(sh_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_3(sha, i32, env, i32, i32)
|
||||
DEF_HELPER_2(sha_h, i32, i32, i32)
|
||||
/* merge/split/parity */
|
||||
DEF_HELPER_FLAGS_2(bmerge, TCG_CALL_NO_RWG_SE, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_1(bsplit, TCG_CALL_NO_RWG_SE, i64, i32)
|
||||
DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
|
||||
/* float */
|
||||
DEF_HELPER_1(unpack, i64, i32)
|
||||
/* dvinit */
|
||||
DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
|
||||
DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
|
||||
DEF_HELPER_3(dvinit_h_13, i64, env, i32, i32)
|
||||
DEF_HELPER_3(dvinit_h_131, i64, env, i32, i32)
|
||||
/* mulh */
|
||||
DEF_HELPER_FLAGS_5(mul_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(mulm_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
|
||||
/* CSA */
|
||||
DEF_HELPER_2(call, void, env, i32)
|
||||
DEF_HELPER_1(ret, void, env)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -94,6 +94,8 @@
|
|||
/* B Format */
|
||||
#define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
|
||||
(MASK_BITS_SHIFT(op, 8, 15) << 16))
|
||||
#define MASK_OP_B_DISP24_SEXT(op) (MASK_BITS_SHIFT(op, 16, 31) + \
|
||||
(MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16))
|
||||
/* BIT Format */
|
||||
#define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
|
||||
#define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
|
||||
|
|
@ -114,7 +116,7 @@
|
|||
/* BOL Format */
|
||||
#define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
|
||||
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
|
||||
(MASK_BITS_SHIFT(op, 22, 27) >> 10))
|
||||
(MASK_BITS_SHIFT(op, 22, 27) << 10))
|
||||
#define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
|
||||
(MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
|
||||
(MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
|
||||
|
|
@ -447,10 +449,16 @@ enum {
|
|||
OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
|
||||
/* BOL Format */
|
||||
OPC1_32_BOL_LD_A_LONGOFF = 0x99,
|
||||
OPC1_32_BOL_LD_W_LONFOFF = 0x19,
|
||||
OPC1_32_BOL_LD_W_LONGOFF = 0x19,
|
||||
OPC1_32_BOL_LEA_LONGOFF = 0xd9,
|
||||
OPC1_32_BOL_ST_W_LONGOFF = 0x59,
|
||||
OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
|
||||
OPC1_32_BOL_LD_B_LONGOFF = 0x79, /* 1.6 only */
|
||||
OPC1_32_BOL_LD_BU_LONGOFF = 0x39, /* 1.6 only */
|
||||
OPC1_32_BOL_LD_H_LONGOFF = 0xc9, /* 1.6 only */
|
||||
OPC1_32_BOL_LD_HU_LONGOFF = 0xb9, /* 1.6 only */
|
||||
OPC1_32_BOL_ST_B_LONGOFF = 0xe9, /* 1.6 only */
|
||||
OPC1_32_BOL_ST_H_LONGOFF = 0xf9, /* 1.6 only */
|
||||
/* BRC Format */
|
||||
OPCM_32_BRC_EQ_NEQ = 0xdf,
|
||||
OPCM_32_BRC_GE = 0xff,
|
||||
|
|
@ -487,6 +495,7 @@ enum {
|
|||
OPC1_32_RLC_ADDIH_A = 0x11,
|
||||
OPC1_32_RLC_MFCR = 0x4d,
|
||||
OPC1_32_RLC_MOV = 0x3b,
|
||||
OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */
|
||||
OPC1_32_RLC_MOV_U = 0xbb,
|
||||
OPC1_32_RLC_MOV_H = 0x7b,
|
||||
OPC1_32_RLC_MOVH_A = 0x91,
|
||||
|
|
@ -495,7 +504,7 @@ enum {
|
|||
OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
|
||||
OPCM_32_RR_ACCUMULATOR = 0x0b,
|
||||
OPCM_32_RR_ADRESS = 0x01,
|
||||
OPCM_32_RR_FLOAT = 0x4b,
|
||||
OPCM_32_RR_DIVIDE = 0x4b,
|
||||
OPCM_32_RR_IDIRECT = 0x2d,
|
||||
/* RR1 Format */
|
||||
OPCM_32_RR1_MUL = 0xb3,
|
||||
|
|
@ -1033,8 +1042,8 @@ enum {
|
|||
OPC2_32_RR_MAX_BU = 0x5b,
|
||||
OPC2_32_RR_MAX_H = 0x7a,
|
||||
OPC2_32_RR_MAX_HU = 0x7b,
|
||||
OPC2_32_RR_MIN = 0x19,
|
||||
OPC2_32_RR_MIN_U = 0x18,
|
||||
OPC2_32_RR_MIN = 0x18,
|
||||
OPC2_32_RR_MIN_U = 0x19,
|
||||
OPC2_32_RR_MIN_B = 0x58,
|
||||
OPC2_32_RR_MIN_BU = 0x59,
|
||||
OPC2_32_RR_MIN_H = 0x78,
|
||||
|
|
|
|||
Loading…
Reference in a new issue