CRIS: Add branch-free versions of abs, lsl, lsr and asr.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5546 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -229,41 +229,52 @@ static inline void t_gen_raise_exception(uint32_t index)
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static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
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static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
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{
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{
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int l1;
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TCGv t0, t_31;
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l1 = gen_new_label();
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t0 = tcg_temp_new(TCG_TYPE_TL);
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/* Speculative shift. */
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t_31 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_shl_tl(d, a, b);
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tcg_gen_shl_tl(d, a, b);
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tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(t_31, 31);
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tcg_gen_movi_tl(d, 0);
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tcg_gen_sub_tl(t0, t_31, b);
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gen_set_label(l1);
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tcg_gen_sar_tl(t0, t0, t_31);
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tcg_gen_and_tl(t0, t0, d);
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tcg_gen_xor_tl(d, d, t0);
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tcg_temp_free(t0);
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tcg_temp_free(t_31);
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}
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}
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static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
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static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
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{
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{
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int l1;
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TCGv t0, t_31;
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l1 = gen_new_label();
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t0 = tcg_temp_new(TCG_TYPE_TL);
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/* Speculative shift. */
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t_31 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_shr_tl(d, a, b);
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tcg_gen_shr_tl(d, a, b);
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tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(t_31, 31);
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tcg_gen_movi_tl(d, 0);
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tcg_gen_sub_tl(t0, t_31, b);
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gen_set_label(l1);
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tcg_gen_sar_tl(t0, t0, t_31);
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tcg_gen_and_tl(t0, t0, d);
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tcg_gen_xor_tl(d, d, t0);
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tcg_temp_free(t0);
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tcg_temp_free(t_31);
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}
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}
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static void t_gen_asr(TCGv d, TCGv a, TCGv b)
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static void t_gen_asr(TCGv d, TCGv a, TCGv b)
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{
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{
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int l1;
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TCGv t0, t_31;
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l1 = gen_new_label();
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t0 = tcg_temp_new(TCG_TYPE_TL);
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/* Speculative shift. */
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t_31 = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_sar_tl(d, a, b);
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tcg_gen_sar_tl(d, a, b);
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tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(t_31, 31);
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tcg_gen_sar_tl(d, a, tcg_const_tl(30));
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tcg_gen_sub_tl(t0, t_31, b);
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gen_set_label(l1);
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tcg_gen_sar_tl(t0, t0, t_31);
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tcg_gen_or_tl(d, d, t0);
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tcg_temp_free(t0);
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tcg_temp_free(t_31);
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}
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}
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/* 64-bit signed mul, lower result in d and upper in d2. */
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/* 64-bit signed mul, lower result in d and upper in d2. */
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@ -1777,20 +1788,20 @@ static unsigned int dec_cmp_r(DisasContext *dc)
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static unsigned int dec_abs_r(DisasContext *dc)
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static unsigned int dec_abs_r(DisasContext *dc)
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{
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{
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int l1;
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TCGv t0;
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DIS(fprintf (logfile, "abs $r%u, $r%u\n",
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DIS(fprintf (logfile, "abs $r%u, $r%u\n",
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dc->op1, dc->op2));
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dc->op1, dc->op2));
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cris_cc_mask(dc, CC_MASK_NZ);
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cris_cc_mask(dc, CC_MASK_NZ);
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dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[1]);
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/* TODO: consider a branch free approach. */
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t0 = tcg_temp_new(TCG_TYPE_TL);
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l1 = gen_new_label();
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tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
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tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
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tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
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tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
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tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
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gen_set_label(l1);
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tcg_temp_free(t0);
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cris_alu(dc, CC_OP_MOVE,
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cris_alu(dc, CC_OP_MOVE,
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cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
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cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
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return 2;
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return 2;
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}
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}
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