target-sparc: implement UA2005 ASI_MMU (0x21)
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
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@ -1396,6 +1396,18 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
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ret = env->scratch[i];
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break;
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}
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case ASI_MMU: /* UA2005 Context ID registers */
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switch ((addr >> 3) & 0x3) {
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case 1:
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ret = env->dmmu.mmu_primary_context;
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break;
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case 2:
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ret = env->dmmu.mmu_secondary_context;
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break;
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default:
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cpu_unassigned_access(cs, addr, true, false, 1, size);
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}
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break;
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case ASI_DCACHE_DATA: /* D-cache data */
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case ASI_DCACHE_TAG: /* D-cache tag access */
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case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
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@ -1714,6 +1726,25 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
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env->scratch[i] = val;
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return;
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}
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case ASI_MMU: /* UA2005 Context ID registers */
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{
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switch ((addr >> 3) & 0x3) {
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case 1:
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env->dmmu.mmu_primary_context = val;
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env->immu.mmu_primary_context = val;
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tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_IDX, MMU_KERNEL_IDX, -1);
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break;
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case 2:
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env->dmmu.mmu_secondary_context = val;
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env->immu.mmu_secondary_context = val;
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tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_SECONDARY_IDX,
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MMU_KERNEL_SECONDARY_IDX, -1);
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break;
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default:
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cpu_unassigned_access(cs, addr, true, false, 1, size);
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}
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}
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return;
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case ASI_QUEUE: /* UA2005 CPU mondo queue */
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case ASI_DCACHE_DATA: /* D-cache data */
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case ASI_DCACHE_TAG: /* D-cache tag access */
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