xilinx_timer: Fix writes into TCSR register
The TCSR register has only 11 valid bits. This is now used by the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1 and later to hang when run under qemu-microblaze. Mask valid bits before writing the register to solve the problem. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
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if (value & TCSR_TINT)
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if (value & TCSR_TINT)
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value &= ~TCSR_TINT;
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value &= ~TCSR_TINT;
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xt->regs[addr] = value;
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xt->regs[addr] = value & 0x7ff;
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if (value & TCSR_ENT)
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if (value & TCSR_ENT)
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timer_enable(xt);
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timer_enable(xt);
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break;
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break;
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