target/i386: Cleanup read_crN, write_crN, lmsw
Pull the svm intercept check into the translator. Pull the entire implementation of lmsw into the translator. Push the check for CR8LEG into the regno validation switch. Unify the gen_io_start check between read/write. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210514151342.384376-40-richard.henderson@linaro.org>
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@ -42,9 +42,8 @@ DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl)
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DEF_HELPER_2(iret_real, void, env, int)
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DEF_HELPER_3(iret_protected, void, env, int, int)
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DEF_HELPER_3(lret_protected, void, env, int, int)
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DEF_HELPER_2(read_crN, tl, env, int)
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DEF_HELPER_3(write_crN, void, env, int, tl)
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DEF_HELPER_2(lmsw, void, env, tl)
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DEF_HELPER_FLAGS_2(read_crN, TCG_CALL_NO_RWG, tl, env, int)
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DEF_HELPER_FLAGS_3(write_crN, TCG_CALL_NO_RWG, void, env, int, tl)
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DEF_HELPER_1(clts, void, env)
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#ifndef CONFIG_USER_ONLY
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@ -60,14 +60,6 @@ void helper_cpuid(CPUX86State *env)
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env->regs[R_EDX] = edx;
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}
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void helper_lmsw(CPUX86State *env, target_ulong t0)
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{
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/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
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if already set to one. */
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t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
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helper_write_crN(env, 0, t0);
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}
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void helper_invlpg(CPUX86State *env, target_ulong addr)
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{
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X86CPU *cpu = env_archcpu(env);
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@ -65,7 +65,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
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{
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target_ulong val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC());
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switch (reg) {
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default:
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val = env->cr[reg];
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@ -83,7 +82,6 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC());
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switch (reg) {
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case 0:
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cpu_x86_update_cr0(env, t0);
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@ -7654,13 +7654,22 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]);
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gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64);
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break;
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CASE_MODRM_OP(6): /* lmsw */
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if (!check_cpl0(s)) {
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break;
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}
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gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0);
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gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
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gen_helper_lmsw(cpu_env, s->T0);
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/*
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* Only the 4 lower bits of CR0 are modified.
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* PE cannot be set to zero if already set to one.
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*/
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tcg_gen_ld_tl(s->T1, cpu_env, offsetof(CPUX86State, cr[0]));
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tcg_gen_andi_tl(s->T0, s->T0, 0xf);
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tcg_gen_andi_tl(s->T1, s->T1, ~0xe);
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tcg_gen_or_tl(s->T0, s->T0, s->T1);
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gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0);
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob(s);
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break;
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@ -8034,58 +8043,56 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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modrm = x86_ldub_code(env, s);
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gen_nop_modrm(env, s, modrm);
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break;
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case 0x120: /* mov reg, crN */
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case 0x122: /* mov crN, reg */
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if (check_cpl0(s)) {
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modrm = x86_ldub_code(env, s);
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/* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
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* AMD documentation (24594.pdf) and testing of
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* intel 386 and 486 processors all show that the mod bits
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* are assumed to be 1's, regardless of actual values.
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*/
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rm = (modrm & 7) | REX_B(s);
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reg = ((modrm >> 3) & 7) | REX_R(s);
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if (CODE64(s))
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ot = MO_64;
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else
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ot = MO_32;
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if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
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if (!check_cpl0(s)) {
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break;
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}
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modrm = x86_ldub_code(env, s);
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/*
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* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
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* AMD documentation (24594.pdf) and testing of Intel 386 and 486
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* processors all show that the mod bits are assumed to be 1's,
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* regardless of actual values.
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*/
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rm = (modrm & 7) | REX_B(s);
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reg = ((modrm >> 3) & 7) | REX_R(s);
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switch (reg) {
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case 0:
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if ((prefixes & PREFIX_LOCK) &&
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(s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
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reg = 8;
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}
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switch(reg) {
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case 0:
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case 2:
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case 3:
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case 4:
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case 8:
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gen_update_cc_op(s);
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gen_jmp_im(s, pc_start - s->cs_base);
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if (b & 2) {
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_op_mov_v_reg(s, ot, s->T0, rm);
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gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
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s->T0);
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob(s);
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} else {
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_read_crN(s->T0, cpu_env, tcg_const_i32(reg));
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gen_op_mov_reg_v(s, ot, rm, s->T0);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_jmp(s, s->pc - s->cs_base);
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}
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}
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break;
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default:
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goto unknown_op;
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break;
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case 2:
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case 3:
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case 4:
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break;
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default:
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goto unknown_op;
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}
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ot = (CODE64(s) ? MO_64 : MO_32);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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if (b & 2) {
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gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg);
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gen_op_mov_v_reg(s, ot, s->T0, rm);
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gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0);
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gen_jmp_im(s, s->pc - s->cs_base);
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gen_eob(s);
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} else {
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gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg);
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gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg));
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gen_op_mov_reg_v(s, ot, rm, s->T0);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_jmp(s, s->pc - s->cs_base);
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}
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}
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break;
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case 0x121: /* mov reg, drN */
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case 0x123: /* mov drN, reg */
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if (check_cpl0(s)) {
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