mmu-hash*: Remove permission checking from find_pte{32, 64}()
find_pte{32,64}() are poorly named, since they both find a PTE and do permissions checking of it. This patch makes them only locate a matching PTE, moving the permission checking and other logic to the caller. We rename the resulting search functions ppc_hash{32,64}_htab_lookup(). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -374,19 +374,15 @@ static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
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return -1;
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return -1;
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}
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}
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static int find_pte32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
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target_ulong sr, target_ulong eaddr, int rwx)
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target_ulong sr, target_ulong eaddr,
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ppc_hash_pte32_t *pte)
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{
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{
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hwaddr pteg_off, pte_offset;
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hwaddr pteg_off, pte_offset;
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ppc_hash_pte32_t pte;
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hwaddr hash;
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hwaddr hash;
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uint32_t vsid, pgidx, ptem;
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uint32_t vsid, pgidx, ptem;
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int ret;
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ret = -1; /* No entry found */
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vsid = sr & SR32_VSID;
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vsid = sr & SR32_VSID;
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ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) ||
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((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0;
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
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pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
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hash = vsid ^ pgidx;
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hash = vsid ^ pgidx;
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ptem = (vsid << 7) | (pgidx >> 10);
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ptem = (vsid << 7) | (pgidx >> 10);
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@ -402,7 +398,7 @@ static int find_pte32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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" hash=" TARGET_FMT_plx "\n",
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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pteg_off = get_pteg_offset32(env, hash);
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pteg_off = get_pteg_offset32(env, hash);
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pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, &pte);
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pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
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if (pte_offset == -1) {
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if (pte_offset == -1) {
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/* Secondary PTEG lookup */
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/* Secondary PTEG lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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@ -410,20 +406,10 @@ static int find_pte32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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" hash=" TARGET_FMT_plx "\n", env->htab_base,
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env->htab_mask, vsid, ptem, ~hash);
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env->htab_mask, vsid, ptem, ~hash);
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pteg_off = get_pteg_offset32(env, ~hash);
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pteg_off = get_pteg_offset32(env, ~hash);
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pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, &pte);
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pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
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}
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}
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if (pte_offset != -1) {
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return pte_offset;
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ret = pte_check_hash32(ctx, pte.pte0, pte.pte1, rwx);
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LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
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ctx->raddr, ctx->prot, ret);
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/* Update page flags */
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if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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ppc_hash32_store_hpte1(env, pte_offset, pte.pte1);
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}
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}
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return ret;
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}
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}
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static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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@ -431,6 +417,8 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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{
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{
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int ret;
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int ret;
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target_ulong sr;
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target_ulong sr;
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hwaddr pte_offset;
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ppc_hash_pte32_t pte;
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/* 1. Handle real mode accesses */
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/* 1. Handle real mode accesses */
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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@ -462,7 +450,22 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
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if ((rwx == 2) && ctx->nx) {
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if ((rwx == 2) && ctx->nx) {
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return -3;
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return -3;
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}
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}
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ret = find_pte32(env, ctx, sr, eaddr, rwx);
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/* 6. Locate the PTE in the hash table */
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pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
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if (pte_offset == -1) {
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return -1;
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}
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LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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/* 7. Check access permissions */
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ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) ||
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((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0;
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ret = pte_check_hash32(ctx, pte.pte0, pte.pte1, rwx);
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/* Update page flags */
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if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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ppc_hash32_store_hpte1(env, pte_offset, pte.pte1);
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}
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return ret;
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return ret;
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}
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}
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@ -374,17 +374,14 @@ static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off,
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return -1;
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return -1;
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}
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}
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static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
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ppc_slb_t *slb, target_ulong eaddr, int rwx)
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ppc_slb_t *slb, target_ulong eaddr,
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ppc_hash_pte64_t *pte)
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{
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{
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hwaddr pteg_off, pte_offset;
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hwaddr pteg_off, pte_offset;
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ppc_hash_pte64_t pte;
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uint64_t vsid, pageaddr, ptem;
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uint64_t vsid, pageaddr, ptem;
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hwaddr hash;
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hwaddr hash;
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int segment_bits, target_page_bits;
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int segment_bits, target_page_bits;
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int ret;
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ret = -1; /* No entry found */
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if (slb->vsid & SLB_VSID_B) {
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if (slb->vsid & SLB_VSID_B) {
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
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vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
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@ -396,8 +393,6 @@ static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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target_page_bits = (slb->vsid & SLB_VSID_L)
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target_page_bits = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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ctx->key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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pageaddr = eaddr & ((1ULL << segment_bits)
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pageaddr = eaddr & ((1ULL << segment_bits)
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- (1ULL << target_page_bits));
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- (1ULL << target_page_bits));
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@ -410,21 +405,19 @@ static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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ptem = (slb->vsid & SLB_VSID_PTEM) |
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ptem = (slb->vsid & SLB_VSID_PTEM) |
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((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
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((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
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ret = -1;
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/* Page address translation */
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/* Page address translation */
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
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" hash " TARGET_FMT_plx "\n",
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" hash " TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, hash);
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env->htab_base, env->htab_mask, hash);
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/* Primary PTEG lookup */
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/* Primary PTEG lookup */
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
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" hash=" TARGET_FMT_plx "\n",
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" hash=" TARGET_FMT_plx "\n",
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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env->htab_base, env->htab_mask, vsid, ptem, hash);
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pteg_off = (hash * HASH_PTEG_SIZE_64) & env->htab_mask;
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pteg_off = (hash * HASH_PTEG_SIZE_64) & env->htab_mask;
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pte_offset = ppc_hash64_pteg_search(env, pteg_off, 0, ptem, &pte);
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pte_offset = ppc_hash64_pteg_search(env, pteg_off, 0, ptem, pte);
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if (pte_offset == -1) {
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if (pte_offset == -1) {
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/* Secondary PTEG lookup */
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/* Secondary PTEG lookup */
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
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@ -433,26 +426,10 @@ static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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env->htab_mask, vsid, ptem, ~hash);
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env->htab_mask, vsid, ptem, ~hash);
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pteg_off = (~hash * HASH_PTEG_SIZE_64) & env->htab_mask;
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pteg_off = (~hash * HASH_PTEG_SIZE_64) & env->htab_mask;
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pte_offset = ppc_hash64_pteg_search(env, pteg_off, 1, ptem, &pte);
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pte_offset = ppc_hash64_pteg_search(env, pteg_off, 1, ptem, pte);
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}
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}
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if (pte_offset != -1) {
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return pte_offset;
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ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx);
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LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
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ctx->raddr, ctx->prot, ret);
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/* Update page flags */
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if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
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}
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}
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
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if (target_page_bits != TARGET_PAGE_BITS) {
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ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
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& TARGET_PAGE_MASK;
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}
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return ret;
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}
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}
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static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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@ -460,6 +437,9 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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{
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{
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int ret;
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int ret;
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ppc_slb_t *slb;
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ppc_slb_t *slb;
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hwaddr pte_offset;
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ppc_hash_pte64_t pte;
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int target_page_bits;
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/* 1. Handle real mode accesses */
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/* 1. Handle real mode accesses */
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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@ -482,8 +462,31 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
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return -3;
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return -3;
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}
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}
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ret = find_pte64(env, ctx, slb, eaddr, rwx);
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/* 4. Locate the PTE in the hash table */
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pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
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if (pte_offset == -1) {
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return -1;
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}
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LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
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/* 5. Check access permissions */
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ctx->key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP)
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: (slb->vsid & SLB_VSID_KS));
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ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx);
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/* Update page flags */
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if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) {
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ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);
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}
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/* We have a TLB that saves 4K pages, so let's
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* split a huge page to 4k chunks */
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target_page_bits = (slb->vsid & SLB_VSID_L)
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? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
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if (target_page_bits != TARGET_PAGE_BITS) {
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ctx->raddr |= (eaddr & ((1 << target_page_bits) - 1))
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& TARGET_PAGE_MASK;
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}
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return ret;
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return ret;
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}
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}
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