From 7fb6577b130c615e42e1ccf8dad69c27c3eef085 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 1 Feb 2011 15:51:28 +0100 Subject: [PATCH] ahci: split ICH and AHCI even more Sebastian's patch already did a pretty good job at splitting up ICH-9 AHCI code and the AHCI core. We need some more though. Copyright was missing, the lspci dump belongs to ICH-9, we don't need the AHCI core to have its own qdev device duplicate. So let's split them a bit more in this patch, making things easier to read an understand. Signed-off-by: Alexander Graf Signed-off-by: Kevin Wolf --- hw/ide/ahci.c | 110 -------------------------------------------------- hw/ide/ich.c | 90 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 88 insertions(+), 112 deletions(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 28412d09aa..6822046859 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -19,47 +19,6 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . * - * - * lspci dump of a ICH-9 real device in IDE mode (hopefully close enough): - * - * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0]) - * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] - * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ - * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- - * Capabilities: [b0] Vendor Specific Information - * Kernel driver in use: ahci - * Kernel modules: ahci - * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00 - * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 - * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29 - * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 - * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 - * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 - * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00 - * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00 - * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00 - * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 - * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 - * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 - * */ #include @@ -1155,72 +1114,3 @@ void ahci_reset(void *opaque) ahci_reset_port(&d->ahci, i); } } - -static int pci_ahci_init(PCIDevice *dev) -{ - struct AHCIPCIState *d; - d = DO_UPCAST(struct AHCIPCIState, card, dev); - - pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL); - pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR); - - pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA); - pci_config_set_revision(d->card.config, 0x02); - pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1); - - d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ - d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ - pci_config_set_interrupt_pin(d->card.config, 1); - - /* XXX Software should program this register */ - d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ - - qemu_register_reset(ahci_reset, d); - - /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ - pci_register_bar(&d->card, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY, - ahci_pci_map); - - msi_init(dev, 0x50, 1, true, false); - - ahci_init(&d->ahci, &dev->qdev); - d->ahci.irq = d->card.irq[0]; - - return 0; -} - -static int pci_ahci_uninit(PCIDevice *dev) -{ - struct AHCIPCIState *d; - d = DO_UPCAST(struct AHCIPCIState, card, dev); - - if (msi_enabled(dev)) { - msi_uninit(dev); - } - - qemu_unregister_reset(ahci_reset, d); - - return 0; -} - -static void pci_ahci_write_config(PCIDevice *pci, uint32_t addr, - uint32_t val, int len) -{ - pci_default_write_config(pci, addr, val, len); - msi_write_config(pci, addr, val, len); -} - -static PCIDeviceInfo ahci_info = { - .qdev.name = "ahci", - .qdev.size = sizeof(AHCIPCIState), - .init = pci_ahci_init, - .exit = pci_ahci_uninit, - .config_write = pci_ahci_write_config, -}; - -static void ahci_pci_register_devices(void) -{ - pci_qdev_register(&ahci_info); -} - -device_init(ahci_pci_register_devices) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 9868b73592..70cb766990 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -1,3 +1,65 @@ +/* + * QEMU ICH Emulation + * + * Copyright (c) 2010 Sebastian Herbszt + * Copyright (c) 2010 Alexander Graf + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + * + * lspci dump of a ICH-9 real device + * + * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0]) + * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] + * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- + * Capabilities: [b0] Vendor Specific Information + * Kernel driver in use: ahci + * Kernel modules: ahci + * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00 + * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00 + * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29 + * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00 + * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 + * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 + * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00 + * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00 + * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00 + * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00 + * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + * + */ + #include #include #include @@ -11,7 +73,7 @@ #include #include -static int pci_ich9_ahci_initfn(PCIDevice *dev) +static int pci_ich9_ahci_init(PCIDevice *dev) { struct AHCIPCIState *d; d = DO_UPCAST(struct AHCIPCIState, card, dev); @@ -44,11 +106,35 @@ static int pci_ich9_ahci_initfn(PCIDevice *dev) return 0; } +static int pci_ich9_uninit(PCIDevice *dev) +{ + struct AHCIPCIState *d; + d = DO_UPCAST(struct AHCIPCIState, card, dev); + + if (msi_enabled(dev)) { + msi_uninit(dev); + } + + qemu_unregister_reset(ahci_reset, d); + + return 0; +} + +static void pci_ich9_write_config(PCIDevice *pci, uint32_t addr, + uint32_t val, int len) +{ + pci_default_write_config(pci, addr, val, len); + msi_write_config(pci, addr, val, len); +} + static PCIDeviceInfo ich_ahci_info[] = { { .qdev.name = "ich9-ahci", + .qdev.alias = "ahci", .qdev.size = sizeof(AHCIPCIState), - .init = pci_ich9_ahci_initfn, + .init = pci_ich9_ahci_init, + .exit = pci_ich9_uninit, + .config_write = pci_ich9_write_config, },{ /* end of list */ }