target/arm: Correct store of FPSCR value via FPCXT_S
In commit 64f863baee
we implemented the v8.1M FPCXT_S register,
but we got the write behaviour wrong. On read, this register reads
bits [27:0] of FPSCR plus the CONTROL.SFPA bit. On write, it doesn't
just write back those bits -- it writes a value to the whole FPSCR,
whose upper 4 bits are zeroes.
We also incorrectly implemented the write-to-FPSCR as a simple store
to vfp.xregs; this skips the "update the softfloat flags" part of
the vfp_set_fpscr helper so the value would read back correctly but
not actually take effect.
Fix both of these things by doing a complete write to the FPSCR
using the helper function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201210201433.26262-3-peter.maydell@linaro.org
This commit is contained in:
parent
5b7d63706e
commit
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@ -723,8 +723,11 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
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}
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case ARM_VFP_FPCXT_S:
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{
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TCGv_i32 sfpa, control, fpscr;
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/* Set FPSCR[27:0] and CONTROL.SFPA from value */
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TCGv_i32 sfpa, control;
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/*
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* Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes
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* bits [27:0] from value and zeroes bits [31:28].
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*/
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tmp = loadfn(s, opaque);
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sfpa = tcg_temp_new_i32();
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tcg_gen_shri_i32(sfpa, tmp, 31);
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@ -732,11 +735,8 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
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tcg_gen_deposit_i32(control, control, sfpa,
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R_V7M_CONTROL_SFPA_SHIFT, 1);
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store_cpu_field(control, v7m.control[M_REG_S]);
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fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
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tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
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tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
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tcg_gen_or_i32(fpscr, fpscr, tmp);
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store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
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gen_helper_vfp_set_fpscr(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(sfpa);
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break;
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