From 80189035de73f30e42a7f933c45cccfc4b0c56e9 Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Mon, 31 Mar 2014 16:03:57 -0500 Subject: [PATCH] target-ppc: Define Endian-Correct Accessors for VSR Field Access This change defines accessors for VSR doubleword and word fields that are correct from a host Endian perspective. This allows code to use the Power ISA indexing numbers in code. For example, the xscvdpsxws instruction has a target VSR that looks like this: 0 32 64 127 +-----------+--------+-----------+-----------+ | undefined | SW | undefined | undefined | +-----------+--------+-----------+-----------+ VSX helper code will use VsrW(1) to access this field. Signed-off-by: Tom Musta Tested-by: Tom Musta Signed-off-by: Alexander Graf --- target-ppc/fpu_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 691d5724ed..d79aae9dbe 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1782,6 +1782,14 @@ typedef union _ppc_vsr_t { float64 f64[2]; } ppc_vsr_t; +#if defined(HOST_WORDS_BIGENDIAN) +#define VsrW(i) u32[i] +#define VsrD(i) u64[i] +#else +#define VsrW(i) u32[3-(i)] +#define VsrD(i) u64[1-(i)] +#endif + static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) {