vga: add mmio bar to standard vga
This patch adds a mmio bar to the qemu standard vga which allows to access the standard vga registers and bochs dispi interface registers via mmio. Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
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0d0302e203
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803ff052b6
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@ -379,6 +379,10 @@ static QEMUMachine pc_machine_v1_3 = {
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.driver = "qxl-vga",\
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.driver = "qxl-vga",\
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.property = "revision",\
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.property = "revision",\
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.value = stringify(3),\
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.value = stringify(3),\
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},{\
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.driver = "VGA",\
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.property = "mmio",\
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.value = "off",\
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}
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}
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static QEMUMachine pc_machine_v1_2 = {
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static QEMUMachine pc_machine_v1_2 = {
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108
hw/vga-pci.c
108
hw/vga-pci.c
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@ -29,9 +29,23 @@
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#include "qemu-timer.h"
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#include "qemu-timer.h"
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#include "loader.h"
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#include "loader.h"
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#define PCI_VGA_IOPORT_OFFSET 0x400
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#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
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#define PCI_VGA_BOCHS_OFFSET 0x500
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#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
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#define PCI_VGA_MMIO_SIZE 0x1000
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enum vga_pci_flags {
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PCI_VGA_FLAG_ENABLE_MMIO = 1,
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};
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typedef struct PCIVGAState {
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typedef struct PCIVGAState {
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PCIDevice dev;
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PCIDevice dev;
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VGACommonState vga;
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VGACommonState vga;
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uint32_t flags;
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MemoryRegion mmio;
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MemoryRegion ioport;
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MemoryRegion bochs;
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} PCIVGAState;
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} PCIVGAState;
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static const VMStateDescription vmstate_vga_pci = {
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static const VMStateDescription vmstate_vga_pci = {
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@ -46,6 +60,84 @@ static const VMStateDescription vmstate_vga_pci = {
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}
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}
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};
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};
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static uint64_t pci_vga_ioport_read(void *ptr, target_phys_addr_t addr,
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unsigned size)
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{
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PCIVGAState *d = ptr;
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uint64_t ret = 0;
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switch (size) {
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case 1:
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ret = vga_ioport_read(&d->vga, addr);
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break;
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case 2:
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ret = vga_ioport_read(&d->vga, addr);
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ret |= vga_ioport_read(&d->vga, addr+1) << 8;
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break;
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}
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return ret;
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}
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static void pci_vga_ioport_write(void *ptr, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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switch (size) {
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case 1:
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vga_ioport_write(&d->vga, addr, val);
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break;
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case 2:
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/*
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* Update bytes in little endian order. Allows to update
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* indexed registers with a single word write because the
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* index byte is updated first.
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*/
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vga_ioport_write(&d->vga, addr, val & 0xff);
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vga_ioport_write(&d->vga, addr+1, (val >> 8) & 0xff);
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break;
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}
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}
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static const MemoryRegionOps pci_vga_ioport_ops = {
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.read = pci_vga_ioport_read,
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.write = pci_vga_ioport_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t pci_vga_bochs_read(void *ptr, target_phys_addr_t addr,
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unsigned size)
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{
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PCIVGAState *d = ptr;
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int index = addr >> 1;
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vbe_ioport_write_index(&d->vga, 0, index);
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return vbe_ioport_read_data(&d->vga, 0);
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}
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static void pci_vga_bochs_write(void *ptr, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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int index = addr >> 1;
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vbe_ioport_write_index(&d->vga, 0, index);
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vbe_ioport_write_data(&d->vga, 0, val);
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}
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static const MemoryRegionOps pci_vga_bochs_ops = {
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.read = pci_vga_bochs_read,
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.write = pci_vga_bochs_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 2,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int pci_std_vga_initfn(PCIDevice *dev)
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static int pci_std_vga_initfn(PCIDevice *dev)
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{
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{
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PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
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PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
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@ -61,6 +153,21 @@ static int pci_std_vga_initfn(PCIDevice *dev)
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/* XXX: VGA_RAM_SIZE must be a power of two */
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/* XXX: VGA_RAM_SIZE must be a power of two */
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pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
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pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
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/* mmio bar for vga register access */
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if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
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memory_region_init(&d->mmio, "vga.mmio", 4096);
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memory_region_init_io(&d->ioport, &pci_vga_ioport_ops, d,
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"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
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memory_region_init_io(&d->bochs, &pci_vga_bochs_ops, d,
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"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
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memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
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&d->ioport);
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memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
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&d->bochs);
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pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
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}
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if (!dev->rom_bar) {
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if (!dev->rom_bar) {
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/* compatibility with pc-0.13 and older */
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/* compatibility with pc-0.13 and older */
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vga_init_vbe(s, pci_address_space(dev));
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vga_init_vbe(s, pci_address_space(dev));
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@ -71,6 +178,7 @@ static int pci_std_vga_initfn(PCIDevice *dev)
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static Property vga_pci_properties[] = {
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static Property vga_pci_properties[] = {
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DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
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DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
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DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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6
hw/vga.c
6
hw/vga.c
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@ -591,7 +591,7 @@ static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
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return val;
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return val;
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}
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}
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static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
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uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
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{
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{
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VGACommonState *s = opaque;
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VGACommonState *s = opaque;
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uint32_t val;
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uint32_t val;
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@ -627,13 +627,13 @@ static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
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return val;
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return val;
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}
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}
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static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
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void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
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{
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{
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VGACommonState *s = opaque;
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VGACommonState *s = opaque;
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s->vbe_index = val;
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s->vbe_index = val;
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}
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}
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static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
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void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
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{
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{
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VGACommonState *s = opaque;
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VGACommonState *s = opaque;
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@ -208,7 +208,13 @@ void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
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void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp);
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void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp);
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int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
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int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
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#ifdef CONFIG_BOCHS_VBE
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void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
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void vga_init_vbe(VGACommonState *s, MemoryRegion *address_space);
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uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr);
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void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val);
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void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val);
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#endif
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extern const uint8_t sr_mask[8];
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extern const uint8_t sr_mask[8];
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extern const uint8_t gr_mask[16];
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extern const uint8_t gr_mask[16];
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