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target/mips: Add emulation of nanoMIPS 16-bit logic instructions

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Add emulation of NOT16, AND16, XOR16, OR16 instructions.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Yongbok Kim 2018-08-02 16:16:11 +02:00 committed by Aleksandar Markovic
parent 8bdb7029c3
commit 80845edf37
1 changed files with 38 additions and 0 deletions
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38
target/mips/translate.c
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@ -16760,6 +16760,37 @@ static inline int decode_gpr_gpr4_zero(int r)
}
/* extraction utilities */
#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
static void gen_pool16c_nanomips_insn(DisasContext *ctx)
{
int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
switch (extract32(ctx->opcode, 2, 2)) {
case NM_NOT16:
gen_logic(ctx, OPC_NOR, rt, rs, 0);
break;
case NM_AND16:
gen_logic(ctx, OPC_AND, rt, rt, rs);
break;
case NM_XOR16:
gen_logic(ctx, OPC_XOR, rt, rt, rs);
break;
case NM_OR16:
gen_logic(ctx, OPC_OR, rt, rt, rs);
break;
}
}
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
@ -16836,6 +16867,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P16C:
switch (ctx->opcode & 1) {
case NM_POOL16C_0:
gen_pool16c_nanomips_insn(ctx);
break;
case NM_LWXS16:
gen_ldxs(ctx, rt, rs, rd);
@ -16910,6 +16942,12 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case NM_ANDI16:
{
uint32_t u = extract32(ctx->opcode, 0, 4);
u = (u == 12) ? 0xff :
(u == 13) ? 0xffff : u;
gen_logic_imm(ctx, OPC_ANDI, rt, rs, u);
}
break;
case NM_P16_LB:
offset = extract32(ctx->opcode, 0, 2);