Add definitions for Freescale PowerPC implementations,
ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores. Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3681 c046a42c-6fe2-441c-8c8c-71466251a162
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109
target-ppc/cpu.h
109
target-ppc/cpu.h
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@ -845,27 +845,27 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_BOOKE_DEAR (0x03D)
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#define SPR_BOOKE_DEAR (0x03D)
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#define SPR_BOOKE_ESR (0x03E)
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#define SPR_BOOKE_ESR (0x03E)
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#define SPR_BOOKE_IVPR (0x03F)
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#define SPR_BOOKE_IVPR (0x03F)
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#define SPR_8xx_EIE (0x050)
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#define SPR_MPC_EIE (0x050)
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#define SPR_8xx_EID (0x051)
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#define SPR_MPC_EID (0x051)
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#define SPR_8xx_NRE (0x052)
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#define SPR_MPC_NRI (0x052)
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#define SPR_CTRL (0x088)
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#define SPR_CTRL (0x088)
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#define SPR_58x_CMPA (0x090)
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#define SPR_MPC_CMPA (0x090)
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#define SPR_58x_CMPB (0x091)
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#define SPR_MPC_CMPB (0x091)
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#define SPR_58x_CMPC (0x092)
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#define SPR_MPC_CMPC (0x092)
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#define SPR_58x_CMPD (0x093)
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#define SPR_MPC_CMPD (0x093)
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#define SPR_58x_ICR (0x094)
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#define SPR_MPC_ECR (0x094)
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#define SPR_58x_DER (0x094)
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#define SPR_MPC_DER (0x095)
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#define SPR_58x_COUNTA (0x096)
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#define SPR_MPC_COUNTA (0x096)
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#define SPR_58x_COUNTB (0x097)
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#define SPR_MPC_COUNTB (0x097)
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#define SPR_UCTRL (0x098)
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#define SPR_UCTRL (0x098)
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#define SPR_58x_CMPE (0x098)
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#define SPR_MPC_CMPE (0x098)
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#define SPR_58x_CMPF (0x099)
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#define SPR_MPC_CMPF (0x099)
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#define SPR_58x_CMPG (0x09A)
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#define SPR_MPC_CMPG (0x09A)
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#define SPR_58x_CMPH (0x09B)
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#define SPR_MPC_CMPH (0x09B)
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#define SPR_58x_LCTRL1 (0x09C)
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#define SPR_MPC_LCTRL1 (0x09C)
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#define SPR_58x_LCTRL2 (0x09D)
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#define SPR_MPC_LCTRL2 (0x09D)
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#define SPR_58x_ICTRL (0x09E)
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#define SPR_MPC_ICTRL (0x09E)
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#define SPR_58x_BAR (0x09F)
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#define SPR_MPC_BAR (0x09F)
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#define SPR_VRSAVE (0x100)
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#define SPR_VRSAVE (0x100)
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#define SPR_USPRG0 (0x100)
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#define SPR_USPRG0 (0x100)
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#define SPR_USPRG1 (0x101)
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#define SPR_USPRG1 (0x101)
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@ -943,12 +943,15 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_BOOKE_IVOR14 (0x19E)
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#define SPR_BOOKE_IVOR14 (0x19E)
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#define SPR_BOOKE_IVOR15 (0x19F)
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#define SPR_BOOKE_IVOR15 (0x19F)
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#define SPR_BOOKE_SPEFSCR (0x200)
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#define SPR_BOOKE_SPEFSCR (0x200)
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#define SPR_E500_BBEAR (0x201)
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#define SPR_Exxx_BBEAR (0x201)
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#define SPR_E500_BBTAR (0x202)
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#define SPR_Exxx_BBTAR (0x202)
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#define SPR_Exxx_L1CFG0 (0x203)
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#define SPR_Exxx_NPIDR (0x205)
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#define SPR_ATBL (0x20E)
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#define SPR_ATBL (0x20E)
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#define SPR_ATBU (0x20F)
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#define SPR_ATBU (0x20F)
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#define SPR_IBAT0U (0x210)
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#define SPR_IBAT0U (0x210)
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#define SPR_BOOKE_IVOR32 (0x210)
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#define SPR_BOOKE_IVOR32 (0x210)
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#define SPR_RCPU_MI_GRA (0x210)
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#define SPR_IBAT0L (0x211)
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#define SPR_IBAT0L (0x211)
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#define SPR_BOOKE_IVOR33 (0x211)
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#define SPR_BOOKE_IVOR33 (0x211)
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#define SPR_IBAT1U (0x212)
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#define SPR_IBAT1U (0x212)
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@ -958,12 +961,11 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_IBAT2U (0x214)
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#define SPR_IBAT2U (0x214)
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#define SPR_BOOKE_IVOR36 (0x214)
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#define SPR_BOOKE_IVOR36 (0x214)
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#define SPR_IBAT2L (0x215)
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#define SPR_IBAT2L (0x215)
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#define SPR_E500_L1CFG0 (0x215)
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#define SPR_BOOKE_IVOR37 (0x215)
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#define SPR_BOOKE_IVOR37 (0x215)
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#define SPR_IBAT3U (0x216)
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#define SPR_IBAT3U (0x216)
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#define SPR_E500_L1CFG1 (0x216)
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#define SPR_IBAT3L (0x217)
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#define SPR_IBAT3L (0x217)
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#define SPR_DBAT0U (0x218)
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#define SPR_DBAT0U (0x218)
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#define SPR_RCPU_L2U_GRA (0x218)
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#define SPR_DBAT0L (0x219)
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#define SPR_DBAT0L (0x219)
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#define SPR_DBAT1U (0x21A)
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#define SPR_DBAT1U (0x21A)
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#define SPR_DBAT1L (0x21B)
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#define SPR_DBAT1L (0x21B)
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@ -972,23 +974,35 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_DBAT3U (0x21E)
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#define SPR_DBAT3U (0x21E)
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#define SPR_DBAT3L (0x21F)
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#define SPR_DBAT3L (0x21F)
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#define SPR_IBAT4U (0x230)
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#define SPR_IBAT4U (0x230)
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#define SPR_RPCU_BBCMCR (0x230)
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#define SPR_MPC_IC_CST (0x230)
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#define SPR_Exxx_CTXCR (0x230)
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#define SPR_IBAT4L (0x231)
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#define SPR_IBAT4L (0x231)
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#define SPR_MPC_IC_ADR (0x231)
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#define SPR_Exxx_DBCR3 (0x231)
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#define SPR_IBAT5U (0x232)
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#define SPR_IBAT5U (0x232)
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#define SPR_MPC_IC_DAT (0x232)
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#define SPR_Exxx_DBCNT (0x232)
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#define SPR_IBAT5L (0x233)
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#define SPR_IBAT5L (0x233)
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#define SPR_IBAT6U (0x234)
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#define SPR_IBAT6U (0x234)
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#define SPR_IBAT6L (0x235)
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#define SPR_IBAT6L (0x235)
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#define SPR_IBAT7U (0x236)
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#define SPR_IBAT7U (0x236)
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#define SPR_IBAT7L (0x237)
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#define SPR_IBAT7L (0x237)
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#define SPR_DBAT4U (0x238)
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#define SPR_DBAT4U (0x238)
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#define SPR_RCPU_L2U_MCR (0x238)
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#define SPR_MPC_DC_CST (0x238)
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#define SPR_Exxx_ALTCTXCR (0x238)
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#define SPR_DBAT4L (0x239)
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#define SPR_DBAT4L (0x239)
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#define SPR_MPC_DC_ADR (0x239)
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#define SPR_DBAT5U (0x23A)
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#define SPR_DBAT5U (0x23A)
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#define SPR_BOOKE_MCSRR0 (0x23A)
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#define SPR_BOOKE_MCSRR0 (0x23A)
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#define SPR_MPC_DC_DAT (0x23A)
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#define SPR_DBAT5L (0x23B)
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#define SPR_DBAT5L (0x23B)
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#define SPR_BOOKE_MCSRR1 (0x23B)
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#define SPR_BOOKE_MCSRR1 (0x23B)
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#define SPR_DBAT6U (0x23C)
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#define SPR_DBAT6U (0x23C)
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#define SPR_BOOKE_MCSR (0x23C)
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#define SPR_BOOKE_MCSR (0x23C)
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#define SPR_DBAT6L (0x23D)
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#define SPR_DBAT6L (0x23D)
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#define SPR_E500_MCAR (0x23D)
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#define SPR_Exxx_MCAR (0x23D)
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#define SPR_DBAT7U (0x23E)
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#define SPR_DBAT7U (0x23E)
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#define SPR_BOOKE_DSRR0 (0x23E)
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#define SPR_BOOKE_DSRR0 (0x23E)
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#define SPR_DBAT7L (0x23F)
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#define SPR_DBAT7L (0x23F)
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@ -1000,30 +1014,54 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_BOOKE_MAS2 (0x272)
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#define SPR_BOOKE_MAS2 (0x272)
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#define SPR_BOOKE_MAS3 (0x273)
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#define SPR_BOOKE_MAS3 (0x273)
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#define SPR_BOOKE_MAS4 (0x274)
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#define SPR_BOOKE_MAS4 (0x274)
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#define SPR_BOOKE_MAS5 (0x275)
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#define SPR_BOOKE_MAS6 (0x276)
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#define SPR_BOOKE_MAS6 (0x276)
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#define SPR_BOOKE_PID1 (0x279)
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#define SPR_BOOKE_PID1 (0x279)
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#define SPR_BOOKE_PID2 (0x27A)
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#define SPR_BOOKE_PID2 (0x27A)
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#define SPR_MPC_DPDR (0x280)
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#define SPR_MPC_IMMR (0x288)
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#define SPR_BOOKE_TLB0CFG (0x2B0)
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#define SPR_BOOKE_TLB0CFG (0x2B0)
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#define SPR_BOOKE_TLB1CFG (0x2B1)
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#define SPR_BOOKE_TLB1CFG (0x2B1)
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#define SPR_BOOKE_TLB2CFG (0x2B2)
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#define SPR_BOOKE_TLB2CFG (0x2B2)
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#define SPR_BOOKE_TLB3CFG (0x2B3)
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#define SPR_BOOKE_TLB3CFG (0x2B3)
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#define SPR_BOOKE_EPR (0x2BE)
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#define SPR_BOOKE_EPR (0x2BE)
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#define SPR_PERF0 (0x300)
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#define SPR_PERF0 (0x300)
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#define SPR_RCPU_MI_RBA0 (0x300)
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#define SPR_MPC_MI_CTR (0x300)
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#define SPR_PERF1 (0x301)
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#define SPR_PERF1 (0x301)
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#define SPR_RCPU_MI_RBA1 (0x301)
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#define SPR_PERF2 (0x302)
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#define SPR_PERF2 (0x302)
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#define SPR_RCPU_MI_RBA2 (0x302)
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#define SPR_MPC_MI_AP (0x302)
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#define SPR_PERF3 (0x303)
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#define SPR_PERF3 (0x303)
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#define SPR_RCPU_MI_RBA3 (0x303)
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#define SPR_MPC_MI_EPN (0x303)
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#define SPR_PERF4 (0x304)
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#define SPR_PERF4 (0x304)
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#define SPR_PERF5 (0x305)
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#define SPR_PERF5 (0x305)
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#define SPR_MPC_MI_TWC (0x305)
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#define SPR_PERF6 (0x306)
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#define SPR_PERF6 (0x306)
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#define SPR_MPC_MI_RPN (0x306)
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#define SPR_PERF7 (0x307)
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#define SPR_PERF7 (0x307)
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#define SPR_PERF8 (0x308)
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#define SPR_PERF8 (0x308)
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#define SPR_RCPU_L2U_RBA0 (0x308)
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#define SPR_MPC_MD_CTR (0x308)
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#define SPR_PERF9 (0x309)
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#define SPR_PERF9 (0x309)
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#define SPR_RCPU_L2U_RBA1 (0x309)
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#define SPR_MPC_MD_CASID (0x309)
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#define SPR_PERFA (0x30A)
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#define SPR_PERFA (0x30A)
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#define SPR_RCPU_L2U_RBA2 (0x30A)
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#define SPR_MPC_MD_AP (0x30A)
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#define SPR_PERFB (0x30B)
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#define SPR_PERFB (0x30B)
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#define SPR_RCPU_L2U_RBA3 (0x30B)
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#define SPR_MPC_MD_EPN (0x30B)
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#define SPR_PERFC (0x30C)
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#define SPR_PERFC (0x30C)
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#define SPR_MPC_MD_TWB (0x30C)
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#define SPR_PERFD (0x30D)
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#define SPR_PERFD (0x30D)
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#define SPR_MPC_MD_TWC (0x30D)
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#define SPR_PERFE (0x30E)
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#define SPR_PERFE (0x30E)
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#define SPR_MPC_MD_RPN (0x30E)
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#define SPR_PERFF (0x30F)
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#define SPR_PERFF (0x30F)
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#define SPR_MPC_MD_TW (0x30F)
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#define SPR_UPERF0 (0x310)
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#define SPR_UPERF0 (0x310)
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#define SPR_UPERF1 (0x311)
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#define SPR_UPERF1 (0x311)
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#define SPR_UPERF2 (0x312)
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#define SPR_UPERF2 (0x312)
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@ -1040,6 +1078,20 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_UPERFD (0x31D)
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#define SPR_UPERFD (0x31D)
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#define SPR_UPERFE (0x31E)
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#define SPR_UPERFE (0x31E)
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#define SPR_UPERFF (0x31F)
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#define SPR_UPERFF (0x31F)
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#define SPR_RCPU_MI_RA0 (0x320)
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#define SPR_MPC_MI_DBCAM (0x320)
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#define SPR_RCPU_MI_RA1 (0x321)
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#define SPR_MPC_MI_DBRAM0 (0x321)
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#define SPR_RCPU_MI_RA2 (0x322)
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#define SPR_MPC_MI_DBRAM1 (0x322)
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#define SPR_RCPU_MI_RA3 (0x323)
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#define SPR_RCPU_L2U_RA0 (0x328)
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#define SPR_MPC_MD_DBCAM (0x328)
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#define SPR_RCPU_L2U_RA1 (0x329)
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#define SPR_MPC_MD_DBRAM0 (0x329)
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#define SPR_RCPU_L2U_RA2 (0x32A)
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#define SPR_MPC_MD_DBRAM1 (0x32A)
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#define SPR_RCPU_L2U_RA3 (0x32B)
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#define SPR_440_INV0 (0x370)
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#define SPR_440_INV0 (0x370)
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#define SPR_440_INV1 (0x371)
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#define SPR_440_INV1 (0x371)
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#define SPR_440_INV2 (0x372)
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#define SPR_440_INV2 (0x372)
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@ -1164,17 +1216,17 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_IABR (0x3F2)
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#define SPR_IABR (0x3F2)
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#define SPR_40x_DBCR0 (0x3F2)
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#define SPR_40x_DBCR0 (0x3F2)
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#define SPR_601_HID2 (0x3F2)
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#define SPR_601_HID2 (0x3F2)
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#define SPR_E500_L1CSR0 (0x3F2)
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#define SPR_Exxx_L1CSR0 (0x3F2)
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#define SPR_ICTRL (0x3F3)
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#define SPR_ICTRL (0x3F3)
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#define SPR_HID2 (0x3F3)
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#define SPR_HID2 (0x3F3)
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#define SPR_E500_L1CSR1 (0x3F3)
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#define SPR_Exxx_L1CSR1 (0x3F3)
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#define SPR_440_DBDR (0x3F3)
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#define SPR_440_DBDR (0x3F3)
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#define SPR_LDSTDB (0x3F4)
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#define SPR_LDSTDB (0x3F4)
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#define SPR_40x_IAC1 (0x3F4)
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#define SPR_40x_IAC1 (0x3F4)
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#define SPR_MMUCSR0 (0x3F4)
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#define SPR_MMUCSR0 (0x3F4)
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#define SPR_DABR (0x3F5)
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#define SPR_DABR (0x3F5)
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#define DABR_MASK (~(target_ulong)0x7)
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#define DABR_MASK (~(target_ulong)0x7)
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#define SPR_E500_BUCSR (0x3F5)
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#define SPR_Exxx_BUCSR (0x3F5)
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#define SPR_40x_IAC2 (0x3F5)
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#define SPR_40x_IAC2 (0x3F5)
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#define SPR_601_HID5 (0x3F5)
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#define SPR_601_HID5 (0x3F5)
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#define SPR_40x_DAC1 (0x3F6)
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#define SPR_40x_DAC1 (0x3F6)
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@ -1188,6 +1240,7 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_L2PMCR (0x3F8)
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#define SPR_L2PMCR (0x3F8)
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#define SPR_750_HID2 (0x3F8)
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#define SPR_750_HID2 (0x3F8)
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#define SPR_620_HID8 (0x3F8)
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#define SPR_620_HID8 (0x3F8)
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#define SPR_Exxx_L1FINV0 (0x3F8)
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#define SPR_L2CR (0x3F9)
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#define SPR_L2CR (0x3F9)
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#define SPR_620_HID9 (0x3F9)
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#define SPR_620_HID9 (0x3F9)
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#define SPR_L3CR (0x3FA)
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#define SPR_L3CR (0x3FA)
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@ -1203,7 +1256,7 @@ static inline int cpu_mmu_index (CPUState *env)
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#define SPR_604_HID13 (0x3FD)
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#define SPR_604_HID13 (0x3FD)
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#define SPR_LT (0x3FE)
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#define SPR_LT (0x3FE)
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#define SPR_THRM3 (0x3FE)
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#define SPR_THRM3 (0x3FE)
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#define SPR_FPECR (0x3FE)
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#define SPR_RCPU_FPECR (0x3FE)
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#define SPR_403_PBL2 (0x3FE)
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#define SPR_403_PBL2 (0x3FE)
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#define SPR_PIR (0x3FF)
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#define SPR_PIR (0x3FF)
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||||||
#define SPR_403_PBU2 (0x3FF)
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#define SPR_403_PBU2 (0x3FF)
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||||||
|
|
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