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target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()

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In preparation of using the decodetree script, explode
gen_msa_branch() as following:

- OPC_BZ_V              -> BxZ_V(EQ)
- OPC_BNZ_V             -> BxZ_V(NE)
- OPC_BZ_[BHWD]         -> BxZ(false)
- OPC_BNZ_[BHWD]        -> BxZ(true)

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201208003702.4088927-10-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-11-30 14:03:31 +01:00
parent 63af5b9018
commit 810fda17c8
1 changed files with 49 additions and 22 deletions
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71
target/mips/translate.c
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@ -28614,49 +28614,76 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt)
tcg_temp_free_i64(t1);
}
static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
{
TCGv_i64 t0;
check_msa_access(ctx);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
return true;
}
t0 = tcg_temp_new_i64();
tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
return true;
}
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
{
check_msa_access(ctx);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
return true;
}
gen_check_zero_element(bcond, df, wt);
if (if_not) {
tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
}
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
return true;
}
static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
int64_t s16 = (int16_t)ctx->opcode;
check_msa_access(ctx);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
gen_reserved_instruction(ctx);
return;
}
switch (op1) {
case OPC_BZ_V:
case OPC_BNZ_V:
{
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);
}
gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
TCG_COND_EQ : TCG_COND_NE);
break;
case OPC_BZ_B:
case OPC_BZ_H:
case OPC_BZ_W:
case OPC_BZ_D:
gen_check_zero_element(bcond, df, wt);
gen_msa_BxZ(ctx, df, wt, s16, false);
break;
case OPC_BNZ_B:
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
gen_check_zero_element(bcond, df, wt);
tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
gen_msa_BxZ(ctx, df, wt, s16, true);
break;
}
ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
}
static void gen_msa_i8(DisasContext *ctx)