Implement user mode for timers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3337 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -47,6 +47,8 @@ do { printf("TIMER: " fmt , ##args); } while (0)
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*
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*
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*/
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*/
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#define MAX_CPUS 16
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typedef struct SLAVIO_TIMERState {
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typedef struct SLAVIO_TIMERState {
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qemu_irq irq;
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qemu_irq irq;
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ptimer_state *timer;
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ptimer_state *timer;
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@ -54,10 +56,13 @@ typedef struct SLAVIO_TIMERState {
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uint64_t limit;
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uint64_t limit;
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int stopped;
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int stopped;
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int mode; // 0 = processor, 1 = user, 2 = system
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int mode; // 0 = processor, 1 = user, 2 = system
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struct SLAVIO_TIMERState *slave[MAX_CPUS];
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uint32_t slave_mode;
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} SLAVIO_TIMERState;
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} SLAVIO_TIMERState;
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#define TIMER_MAXADDR 0x1f
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#define TIMER_MAXADDR 0x1f
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#define TIMER_SIZE (TIMER_MAXADDR + 1)
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#define TIMER_SIZE (TIMER_MAXADDR + 1)
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#define CPU_TIMER_SIZE 0x10
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// Update count, set irq, update expire_time
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// Update count, set irq, update expire_time
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// Convert from ptimer countdown units
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// Convert from ptimer countdown units
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@ -120,7 +125,7 @@ static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
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break;
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break;
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case 4:
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case 4:
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// read user/system mode
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// read user/system mode
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ret = s->mode & 1;
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ret = s->slave_mode;
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break;
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break;
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default:
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default:
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ret = 0;
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ret = 0;
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@ -141,10 +146,20 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
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saddr = (addr & TIMER_MAXADDR) >> 2;
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saddr = (addr & TIMER_MAXADDR) >> 2;
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switch (saddr) {
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switch (saddr) {
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case 0:
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case 0:
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// set limit, reset counter
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if (s->mode == 1) {
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// set user counter limit MSW, reset counter
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qemu_irq_lower(s->irq);
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s->limit &= 0xfffffe00ULL;
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s->limit |= (uint64_t)val << 32;
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if (!s->limit)
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s->limit = 0x7ffffffffffffe00ULL;
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ptimer_set_limit(s->timer, s->limit >> 9, 1);
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break;
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}
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// set limit, reset counter
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reload = 1;
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reload = 1;
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qemu_irq_lower(s->irq);
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qemu_irq_lower(s->irq);
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// fall through
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// fall through
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case 2:
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case 2:
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// set limit without resetting counter
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// set limit without resetting counter
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s->limit = val & 0x7ffffe00ULL;
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s->limit = val & 0x7ffffe00ULL;
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@ -152,6 +167,17 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
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s->limit = 0x7ffffe00ULL;
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s->limit = 0x7ffffe00ULL;
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ptimer_set_limit(s->timer, s->limit >> 9, reload);
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ptimer_set_limit(s->timer, s->limit >> 9, reload);
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break;
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break;
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case 1:
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// set user counter limit LSW, reset counter
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if (s->mode == 1) {
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qemu_irq_lower(s->irq);
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s->limit &= 0x7fffffff00000000ULL;
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s->limit |= val & 0xfffffe00ULL;
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if (!s->limit)
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s->limit = 0x7ffffffffffffe00ULL;
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ptimer_set_limit(s->timer, s->limit >> 9, 1);
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}
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break;
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case 3:
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case 3:
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// start/stop user counter
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// start/stop user counter
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if (s->mode == 1) {
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if (s->mode == 1) {
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@ -167,13 +193,24 @@ static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint3
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break;
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break;
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case 4:
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case 4:
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// bit 0: user (1) or system (0) counter mode
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// bit 0: user (1) or system (0) counter mode
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if (s->mode == 0 || s->mode == 1)
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{
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s->mode = val & 1;
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unsigned int i;
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if (s->mode == 1) {
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qemu_irq_lower(s->irq);
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for (i = 0; i < MAX_CPUS; i++) {
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s->limit = -1ULL;
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if (val & (1 << i)) {
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qemu_irq_lower(s->slave[i]->irq);
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s->slave[i]->limit = -1ULL;
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s->slave[i]->mode = 1;
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} else {
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s->slave[i]->mode = 0;
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}
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ptimer_stop(s->slave[i]->timer);
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ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9,
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1);
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ptimer_run(s->slave[i]->timer, 0);
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}
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s->slave_mode = val & ((1 << MAX_CPUS) - 1);
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}
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}
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ptimer_set_limit(s->timer, s->limit >> 9, 1);
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break;
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break;
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default:
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default:
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break;
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break;
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@ -240,7 +277,8 @@ static void slavio_timer_reset(void *opaque)
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qemu_irq_lower(s->irq);
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qemu_irq_lower(s->irq);
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}
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}
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void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
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static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
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qemu_irq irq, int mode)
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{
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{
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int slavio_timer_io_memory;
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int slavio_timer_io_memory;
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SLAVIO_TIMERState *s;
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SLAVIO_TIMERState *s;
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@ -248,7 +286,7 @@ void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
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s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
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s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
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if (!s)
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if (!s)
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return;
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return s;
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s->irq = irq;
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s->irq = irq;
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s->mode = mode;
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s->mode = mode;
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bh = qemu_bh_new(slavio_timer_irq, s);
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bh = qemu_bh_new(slavio_timer_irq, s);
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@ -257,8 +295,29 @@ void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
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slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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slavio_timer_mem_write, s);
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slavio_timer_mem_write, s);
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cpu_register_physical_memory(addr, TIMER_SIZE, slavio_timer_io_memory);
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if (mode < 2)
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cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
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else
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cpu_register_physical_memory(addr, TIMER_SIZE,
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slavio_timer_io_memory);
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register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
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register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
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qemu_register_reset(slavio_timer_reset, s);
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qemu_register_reset(slavio_timer_reset, s);
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slavio_timer_reset(s);
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slavio_timer_reset(s);
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return s;
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}
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void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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qemu_irq *cpu_irqs)
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{
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SLAVIO_TIMERState *master;
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unsigned int i;
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master = slavio_timer_init(base + 0x10000ULL, master_irq, 2);
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for (i = 0; i < MAX_CPUS; i++) {
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master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
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(i * TARGET_PAGE_SIZE),
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cpu_irqs[i], 0);
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}
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}
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}
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11
hw/sun4m.c
11
hw/sun4m.c
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@ -380,13 +380,10 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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hwdef->nvram_size, 8);
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for (i = 0; i < MAX_CPUS; i++) {
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slavio_timer_init(hwdef->counter_base +
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slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
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(target_phys_addr_t)(i * TARGET_PAGE_SIZE),
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slavio_cpu_irq);
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slavio_cpu_irq[i], 0);
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}
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slavio_timer_init(hwdef->counter_base + 0x10000ULL,
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slavio_irq[hwdef->clock1_irq], 2);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
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slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq]);
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
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3
vl.h
3
vl.h
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@ -1287,7 +1287,8 @@ int load_aout(const char *filename, uint8_t *addr);
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int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
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int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
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/* slavio_timer.c */
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/* slavio_timer.c */
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void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
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void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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qemu_irq *cpu_irqs);
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/* slavio_serial.c */
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/* slavio_serial.c */
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SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
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SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
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