target-arm: A64: add support for 2-src data processing and DIV
This patch adds support for decoding 2-src data processing insns, and the first users, UDIV and SDIV. Signed-off-by: Alexander Graf <agraf@suse.de> [claudio: adapted to new decoder adding the 2-src decoding level, always zero-extend result in 32bit mode] Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -23,3 +23,24 @@
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#include "qemu/host-utils.h"
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#include "qemu/host-utils.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/sysemu.h"
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#include "qemu/bitops.h"
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#include "qemu/bitops.h"
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/* C2.4.7 Multiply and divide */
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/* special cases for 0 and LLONG_MIN are mandated by the standard */
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uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
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{
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if (den == 0) {
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return 0;
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}
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return num / den;
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}
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int64_t HELPER(sdiv64)(int64_t num, int64_t den)
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{
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if (den == 0) {
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return 0;
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}
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if (num == LLONG_MIN && den == -1) {
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return LLONG_MIN;
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}
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return num / den;
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}
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@ -16,3 +16,5 @@
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* You should have received a copy of the GNU Lesser General Public
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
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@ -1050,10 +1050,78 @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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unsupported_encoding(s, insn);
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}
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}
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/* Data-processing (2 source) */
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static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
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unsigned int rm, unsigned int rn, unsigned int rd)
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{
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TCGv_i64 tcg_n, tcg_m, tcg_rd;
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tcg_rd = cpu_reg(s, rd);
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if (!sf && is_signed) {
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tcg_n = new_tmp_a64(s);
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tcg_m = new_tmp_a64(s);
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tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
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tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
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} else {
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tcg_n = read_cpu_reg(s, rn, sf);
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tcg_m = read_cpu_reg(s, rm, sf);
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}
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if (is_signed) {
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gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
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} else {
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gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
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}
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if (!sf) { /* zero extend final result */
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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}
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/* C3.5.8 Data-processing (2 source)
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* 31 30 29 28 21 20 16 15 10 9 5 4 0
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* +----+---+---+-----------------+------+--------+------+------+
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* | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
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* +----+---+---+-----------------+------+--------+------+------+
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*/
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static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
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static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
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{
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{
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unsigned int sf, rm, opcode, rn, rd;
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sf = extract32(insn, 31, 1);
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rm = extract32(insn, 16, 5);
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opcode = extract32(insn, 10, 6);
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rn = extract32(insn, 5, 5);
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rd = extract32(insn, 0, 5);
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if (extract32(insn, 29, 1)) {
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unallocated_encoding(s);
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return;
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}
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switch (opcode) {
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case 2: /* UDIV */
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handle_div(s, false, sf, rm, rn, rd);
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break;
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case 3: /* SDIV */
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handle_div(s, true, sf, rm, rn, rd);
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break;
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case 8: /* LSLV */
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case 9: /* LSRV */
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case 10: /* ASRV */
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case 11: /* RORV */
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case 16:
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case 17:
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case 18:
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case 19:
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case 20:
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case 21:
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case 22:
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case 23: /* CRC32 */
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unsupported_encoding(s, insn);
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unsupported_encoding(s, insn);
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break;
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default:
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unallocated_encoding(s);
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break;
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}
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}
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}
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/* C3.5 Data processing - register */
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/* C3.5 Data processing - register */
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