i386: separate fpu_helper sysemu-only parts
create a separate tcg/sysemu/fpu_helper.c for the sysemu-only parts. For user mode, some small #ifdefs remain in tcg/fpu_helper.c which do not seem worth splitting into their own user-mode module. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210322132800.7470-16-cfontana@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -1817,7 +1817,10 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env);
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int cpu_get_pic_interrupt(CPUX86State *s);
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/* MSDOS compatibility mode FPU exception support */
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void x86_register_ferr_irq(qemu_irq irq);
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void fpu_check_raise_ferr_irq(CPUX86State *s);
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void cpu_set_ignne(void);
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void cpu_clear_ignne(void);
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/* mpx_helper.c */
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void cpu_sync_bndcs_hflags(CPUX86State *env);
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@ -21,17 +21,10 @@
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#include <math.h>
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "fpu/softfloat.h"
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#include "fpu/softfloat-macros.h"
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#include "helper-tcg.h"
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#ifdef CONFIG_SOFTMMU
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#include "hw/irq.h"
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#endif
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/* float macros */
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#define FT0 (env->ft0)
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#define ST0 (env->fpregs[env->fpstt].d)
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@ -75,36 +68,6 @@
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#define floatx80_ln2_d make_floatx80(0x3ffe, 0xb17217f7d1cf79abLL)
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#define floatx80_pi_d make_floatx80(0x4000, 0xc90fdaa22168c234LL)
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#if !defined(CONFIG_USER_ONLY)
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static qemu_irq ferr_irq;
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void x86_register_ferr_irq(qemu_irq irq)
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{
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ferr_irq = irq;
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}
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static void cpu_clear_ignne(void)
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{
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CPUX86State *env = &X86_CPU(first_cpu)->env;
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env->hflags2 &= ~HF2_IGNNE_MASK;
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}
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void cpu_set_ignne(void)
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{
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CPUX86State *env = &X86_CPU(first_cpu)->env;
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env->hflags2 |= HF2_IGNNE_MASK;
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/*
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* We get here in response to a write to port F0h. The chipset should
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* deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
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* cleared, because FERR# and FP_IRQ are two separate pins on real
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* hardware. However, we don't model FERR# as a qemu_irq, so we just
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* do directly what the chipset would do, i.e. deassert FP_IRQ.
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*/
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qemu_irq_lower(ferr_irq);
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}
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#endif
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static inline void fpush(CPUX86State *env)
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{
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env->fpstt = (env->fpstt - 1) & 7;
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@ -202,8 +165,8 @@ static void fpu_raise_exception(CPUX86State *env, uintptr_t retaddr)
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raise_exception_ra(env, EXCP10_COPR, retaddr);
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}
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#if !defined(CONFIG_USER_ONLY)
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else if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
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qemu_irq_raise(ferr_irq);
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else {
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fpu_check_raise_ferr_irq(env);
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}
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#endif
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}
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57
target/i386/tcg/sysemu/fpu_helper.c
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57
target/i386/tcg/sysemu/fpu_helper.c
Normal file
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@ -0,0 +1,57 @@
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/*
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* x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers (sysemu code)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/irq.h"
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static qemu_irq ferr_irq;
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void x86_register_ferr_irq(qemu_irq irq)
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{
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ferr_irq = irq;
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}
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void fpu_check_raise_ferr_irq(CPUX86State *env)
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{
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if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
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qemu_irq_raise(ferr_irq);
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return;
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}
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}
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void cpu_clear_ignne(void)
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{
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CPUX86State *env = &X86_CPU(first_cpu)->env;
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env->hflags2 &= ~HF2_IGNNE_MASK;
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}
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void cpu_set_ignne(void)
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{
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CPUX86State *env = &X86_CPU(first_cpu)->env;
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env->hflags2 |= HF2_IGNNE_MASK;
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/*
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* We get here in response to a write to port F0h. The chipset should
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* deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
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* cleared, because FERR# and FP_IRQ are two separate pins on real
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* hardware. However, we don't model FERR# as a qemu_irq, so we just
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* do directly what the chipset would do, i.e. deassert FP_IRQ.
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*/
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qemu_irq_lower(ferr_irq);
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}
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@ -4,4 +4,5 @@ i386_softmmu_ss.add(when: ['CONFIG_TCG', 'CONFIG_SOFTMMU'], if_true: files(
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'excp_helper.c',
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'bpt_helper.c',
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'misc_helper.c',
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'fpu_helper.c',
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))
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