target-arm: add support for neon vld1.64/vst1.64 instructions
Add support for NEON vld1.64 and vst1.64 instructions. This patch is revised to follow more closely the specification and raises undefined exception if 64bit element size is used for vld2/vst2 or vld4/vst4 instructions. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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2301db4916
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8449623376
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@ -795,6 +795,12 @@ static inline TCGv gen_ld32(TCGv addr, int index)
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tcg_gen_qemu_ld32u(tmp, addr, index);
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tcg_gen_qemu_ld32u(tmp, addr, index);
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return tmp;
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return tmp;
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}
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}
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static inline TCGv_i64 gen_ld64(TCGv addr, int index)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_qemu_ld64(tmp, addr, index);
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return tmp;
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}
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static inline void gen_st8(TCGv val, TCGv addr, int index)
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static inline void gen_st8(TCGv val, TCGv addr, int index)
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{
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{
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tcg_gen_qemu_st8(val, addr, index);
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tcg_gen_qemu_st8(val, addr, index);
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@ -810,6 +816,11 @@ static inline void gen_st32(TCGv val, TCGv addr, int index)
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tcg_gen_qemu_st32(val, addr, index);
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tcg_gen_qemu_st32(val, addr, index);
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dead_tmp(val);
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dead_tmp(val);
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}
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}
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static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
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{
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tcg_gen_qemu_st64(val, addr, index);
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tcg_temp_free_i64(val);
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}
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static inline void gen_set_pc_im(uint32_t val)
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static inline void gen_set_pc_im(uint32_t val)
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{
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{
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@ -3680,6 +3691,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
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int op;
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int op;
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int nregs;
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int nregs;
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int interleave;
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int interleave;
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int spacing;
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int stride;
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int stride;
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int size;
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int size;
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int reg;
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int reg;
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@ -3690,6 +3702,7 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
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TCGv addr;
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TCGv addr;
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TCGv tmp;
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TCGv tmp;
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TCGv tmp2;
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TCGv tmp2;
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TCGv_i64 tmp64;
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if (!vfp_enabled(env))
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if (!vfp_enabled(env))
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return 1;
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return 1;
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@ -3702,10 +3715,13 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
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/* Load store all elements. */
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/* Load store all elements. */
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op = (insn >> 8) & 0xf;
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op = (insn >> 8) & 0xf;
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size = (insn >> 6) & 3;
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size = (insn >> 6) & 3;
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if (op > 10 || size == 3)
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if (op > 10)
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return 1;
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return 1;
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nregs = neon_ls_element_type[op].nregs;
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nregs = neon_ls_element_type[op].nregs;
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interleave = neon_ls_element_type[op].interleave;
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interleave = neon_ls_element_type[op].interleave;
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spacing = neon_ls_element_type[op].spacing;
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if (size == 3 && (interleave | spacing) != 1)
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return 1;
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load_reg_var(s, addr, rn);
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load_reg_var(s, addr, rn);
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stride = (1 << size) * interleave;
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stride = (1 << size) * interleave;
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for (reg = 0; reg < nregs; reg++) {
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for (reg = 0; reg < nregs; reg++) {
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@ -3716,6 +3732,18 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
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load_reg_var(s, addr, rn);
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load_reg_var(s, addr, rn);
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tcg_gen_addi_i32(addr, addr, 1 << size);
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tcg_gen_addi_i32(addr, addr, 1 << size);
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}
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}
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if (size == 3) {
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if (load) {
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tmp64 = gen_ld64(addr, IS_USER(s));
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neon_store_reg64(tmp64, rd);
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tcg_temp_free_i64(tmp64);
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} else {
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tmp64 = tcg_temp_new_i64();
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neon_load_reg64(tmp64, rd);
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gen_st64(tmp64, addr, IS_USER(s));
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}
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tcg_gen_addi_i32(addr, addr, stride);
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} else {
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for (pass = 0; pass < 2; pass++) {
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for (pass = 0; pass < 2; pass++) {
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if (size == 2) {
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if (size == 2) {
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if (load) {
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if (load) {
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@ -3774,7 +3802,8 @@ static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
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}
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}
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}
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}
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}
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}
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rd += neon_ls_element_type[op].spacing;
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}
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rd += spacing;
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}
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}
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stride = nregs * 8;
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stride = nregs * 8;
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} else {
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} else {
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