implement i440 instead of i450 ISA memory mappings to be compatible with Bochs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2177 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -55,63 +55,50 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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static uint32_t isa_page_descs[384 / 4];
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static uint8_t smm_enabled;
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static const uint32_t mar_addresses[15] = {
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0xa0000,
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0xc0000,
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0xc4000,
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0xc8000,
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0xcc000,
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0xd0000,
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0xd4000,
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0xd8000,
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0xdc000,
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0xe0000,
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0xe4000,
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0xe8000,
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0xec000,
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0xf0000,
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0x100000,
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};
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static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
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{
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uint32_t addr;
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// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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switch(r) {
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case 3:
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/* RAM */
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cpu_register_physical_memory(start, end - start,
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start);
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break;
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case 1:
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/* ROM (XXX: not quite correct) */
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cpu_register_physical_memory(start, end - start,
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start | IO_MEM_ROM);
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break;
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case 2:
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case 0:
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/* XXX: should distinguish read/write cases */
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for(addr = start; addr < end; addr += 4096) {
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cpu_register_physical_memory(addr, 4096,
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isa_page_descs[(addr - 0xa0000) >> 12]);
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}
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break;
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}
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}
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static void i440fx_update_memory_mappings(PCIDevice *d)
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{
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int i, r;
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uint32_t start, end, addr;
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uint32_t smram, smbase, smsize;
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uint32_t smram, addr;
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for(i = 0; i < 14; i++) {
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r = (d->config[(i >> 1) + 0x61] >> ((i & 1) * 4)) & 3;
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start = mar_addresses[i];
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end = mar_addresses[i + 1];
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// printf("ISA mapping %08x: %d\n", start, r);
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switch(r) {
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case 3:
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/* RAM */
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cpu_register_physical_memory(start, end - start,
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start);
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break;
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case 2:
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/* ROM (XXX: not quite correct) */
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cpu_register_physical_memory(start, end - start,
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start | IO_MEM_ROM);
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break;
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case 1:
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case 0:
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/* XXX: should distinguish read/write cases */
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for(addr = start; addr < end; addr += 4096) {
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cpu_register_physical_memory(addr, 4096,
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isa_page_descs[(addr - 0xa0000) >> 12]);
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}
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break;
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}
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update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
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for(i = 0; i < 12; i++) {
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r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
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update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
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}
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smram = le32_to_cpu(*(uint32_t *)(d->config + 0x6c));
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if ((smm_enabled && (smram & 0x80000000)) || (smram & (1 << 26))) {
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/* Note: we assume the SMM area is in the 0xa0000-0x100000 range */
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smbase = (smram & 0xffff) << 16;
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smsize = (((smram >> 20) & 0xf) + 1) << 16;
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if (smbase >= 0xa0000 && (smbase + smsize) <= 0x100000) {
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cpu_register_physical_memory(smbase, smsize, smbase);
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smram = d->config[0x72];
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if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
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cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
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} else {
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for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
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cpu_register_physical_memory(addr, 4096,
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isa_page_descs[(addr - 0xa0000) >> 12]);
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}
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}
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}
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@ -142,7 +129,7 @@ static void i440fx_write_config(PCIDevice *d,
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{
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(d, address, val, len);
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if ((address >= 0x61 && address <= 0x67) || address == 0x6c)
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if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
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i440fx_update_memory_mappings(d);
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}
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@ -200,7 +187,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state)
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x00; // header_type
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d->config[0x6c] = 0x0a; /* SMRAM */
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d->config[0x72] = 0x02; /* SMRAM */
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register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d);
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*pi440fx_state = d;
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