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qemu-patch-raspberry4
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target/ppc: do not silence snan in xscvspdpn 

The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmatic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regressions.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211228120310.1957990-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
staging
Matheus Ferst 2022-01-04 07:55:34 +01:00 committed by Cédric Le Goater
parent fbe08667c5
commit 84ade98e87
4 changed files with 42 additions and 8 deletions
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5
target/ppc/fpu_helper.c
View File

@ -2816,10 +2816,7 @@ uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
{
float_status tstat = env->fp_status;
set_float_exception_flags(0, &tstat);
return float32_to_float64(xb >> 32, &tstat);
return helper_todouble(xb >> 32);
}
/*

4
tests/tcg/ppc64/Makefile.target
View File

@ -6,9 +6,9 @@ VPATH += $(SRC_PATH)/tests/tcg/ppc64
VPATH += $(SRC_PATH)/tests/tcg/ppc64le
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER8_VECTOR),)
PPC64_TESTS=bcdsub
PPC64_TESTS=bcdsub non_signalling_xscv
endif
bcdsub: CFLAGS += -mpower8-vector
$(PPC64_TESTS): CFLAGS += -mpower8-vector
PPC64_TESTS += byte_reverse
PPC64_TESTS += mtfsf

4
tests/tcg/ppc64le/Makefile.target
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@ -5,9 +5,9 @@
VPATH += $(SRC_PATH)/tests/tcg/ppc64le
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER8_VECTOR),)
PPC64LE_TESTS=bcdsub
PPC64LE_TESTS=bcdsub non_signalling_xscv
endif
bcdsub: CFLAGS += -mpower8-vector
$(PPC64LE_TESTS): CFLAGS += -mpower8-vector
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
PPC64LE_TESTS += byte_reverse

37
tests/tcg/ppc64le/non_signalling_xscv.c 100644
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@ -0,0 +1,37 @@
#include <stdio.h>
#include <stdint.h>
#include <inttypes.h>
#include <assert.h>
#define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \
do { \
uint64_t th, tl, bh = B_HI, bl = B_LO; \
asm("mtvsrd 0, %2\n\t" \
"mtvsrd 1, %3\n\t" \
"xxmrghd 0, 0, 1\n\t" \
INSN " 0, 0\n\t" \
"mfvsrd %0, 0\n\t" \
"xxswapd 0, 0\n\t" \
"mfvsrd %1, 0\n\t" \
: "=r" (th), "=r" (tl) \
: "r" (bh), "r" (bl) \
: "vs0", "vs1"); \
printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \
"%016" PRIx64 "\n", bh, bl, th, tl); \
assert(th == T_HI && tl == T_LO); \
} while (0)
int main(void)
{
/* SNaN shouldn't be silenced */
TEST("xscvspdpn", 0x7fbfffff00000000ULL, 0x0, 0x7ff7ffffe0000000ULL, 0x0);
TEST("xscvdpspn", 0x7ff7ffffffffffffULL, 0x0, 0x7fbfffff7fbfffffULL, 0x0);
/*
* SNaN inputs having no significant bits in the upper 23 bits of the
* signifcand will return Infinity as the result.
*/
TEST("xscvdpspn", 0x7ff000001fffffffULL, 0x0, 0x7f8000007f800000ULL, 0x0);
return 0;
}