hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -70,3 +70,6 @@ config LOONGSON_LIOINTC
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config SIFIVE_CLINT
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bool
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config SIFIVE_PLIC
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bool
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@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
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specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
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specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
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specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
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specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
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specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
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specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
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specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
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@ -27,9 +27,9 @@
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#include "hw/pci/msi.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/sifive_plic.h"
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#include "target/riscv/cpu.h"
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#include "sysemu/sysemu.h"
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#include "hw/riscv/sifive_plic.h"
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#define RISCV_DEBUG_PLIC 0
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@ -17,6 +17,7 @@ config SIFIVE_E
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_GPIO
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select SIFIVE_PLIC
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select SIFIVE_E_PRCI
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select UNIMP
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@ -28,6 +29,7 @@ config SIFIVE_U
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select SIFIVE_CLINT
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select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select SIFIVE_U_OTP
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select SIFIVE_U_PRCI
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select UNIMP
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@ -38,6 +40,7 @@ config SPIKE
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select HTIF
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_PLIC
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config OPENTITAN
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bool
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@ -58,6 +61,7 @@ config RISCV_VIRT
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select PFLASH_CFI01
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select SIFIVE
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select SIFIVE_CLINT
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select SIFIVE_PLIC
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config MICROCHIP_PFSOC
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bool
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@ -67,4 +71,5 @@ config MICROCHIP_PFSOC
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select UNIMP
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select MCHP_PFSOC_MMUART
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select CADENCE_SDHCI
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@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c'))
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riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
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riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
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riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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@ -48,9 +48,9 @@
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#include "hw/misc/unimp.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/microchip_pfsoc.h"
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#include "hw/intc/sifive_clint.h"
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#include "hw/intc/sifive_plic.h"
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#include "sysemu/sysemu.h"
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/*
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@ -39,11 +39,11 @@
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#include "hw/misc/unimp.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_e.h"
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#include "hw/riscv/boot.h"
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#include "hw/intc/sifive_clint.h"
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#include "hw/intc/sifive_plic.h"
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#include "hw/misc/sifive_e_prci.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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@ -46,11 +46,11 @@
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#include "hw/misc/unimp.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_u.h"
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#include "hw/riscv/boot.h"
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#include "hw/intc/sifive_clint.h"
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#include "hw/intc/sifive_plic.h"
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#include "chardev/char.h"
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#include "net/eth.h"
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#include "sysemu/arch_init.h"
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@ -30,12 +30,12 @@
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_test.h"
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#include "hw/riscv/virt.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/numa.h"
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#include "hw/intc/sifive_clint.h"
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#include "hw/intc/sifive_plic.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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