RISC-V: Support 64 bit start address
Even though the start address in ROM code is declared as a 64 bit address for RV64, it can't be used as upper bits are set to zero in ROM code. Update the ROM code correctly to reflect the 64bit value. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20200701183949.398134-5-atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
dc144fe13d
commit
8590f53661
|
@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
|
||||||
uint32_t fdt_load_addr, void *fdt)
|
uint32_t fdt_load_addr, void *fdt)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
uint32_t start_addr_hi32 = 0x00000000;
|
||||||
|
|
||||||
|
#if defined(TARGET_RISCV64)
|
||||||
|
start_addr_hi32 = start_addr >> 32;
|
||||||
|
#endif
|
||||||
/* reset vector */
|
/* reset vector */
|
||||||
uint32_t reset_vec[10] = {
|
uint32_t reset_vec[10] = {
|
||||||
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
|
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
|
||||||
|
@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
|
||||||
#endif
|
#endif
|
||||||
0x00028067, /* jr t0 */
|
0x00028067, /* jr t0 */
|
||||||
start_addr, /* start: .dword */
|
start_addr, /* start: .dword */
|
||||||
0x00000000,
|
start_addr_hi32,
|
||||||
fdt_load_addr, /* fdt_laddr: .dword */
|
fdt_load_addr, /* fdt_laddr: .dword */
|
||||||
0x00000000,
|
0x00000000,
|
||||||
/* fw_dyn: */
|
/* fw_dyn: */
|
||||||
|
|
|
@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine)
|
||||||
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
||||||
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
|
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
|
||||||
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
|
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
|
||||||
|
uint32_t start_addr_hi32 = 0x00000000;
|
||||||
int i;
|
int i;
|
||||||
uint32_t fdt_load_addr;
|
uint32_t fdt_load_addr;
|
||||||
uint64_t kernel_entry;
|
uint64_t kernel_entry;
|
||||||
|
@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine)
|
||||||
/* Compute the fdt load address in dram */
|
/* Compute the fdt load address in dram */
|
||||||
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
|
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
|
||||||
machine->ram_size, s->fdt);
|
machine->ram_size, s->fdt);
|
||||||
|
#if defined(TARGET_RISCV64)
|
||||||
|
start_addr_hi32 = start_addr >> 32;
|
||||||
|
#endif
|
||||||
|
|
||||||
/* reset vector */
|
/* reset vector */
|
||||||
uint32_t reset_vec[11] = {
|
uint32_t reset_vec[11] = {
|
||||||
|
@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine)
|
||||||
#endif
|
#endif
|
||||||
0x00028067, /* jr t0 */
|
0x00028067, /* jr t0 */
|
||||||
start_addr, /* start: .dword */
|
start_addr, /* start: .dword */
|
||||||
0x00000000,
|
start_addr_hi32,
|
||||||
fdt_load_addr, /* fdt_laddr: .dword */
|
fdt_load_addr, /* fdt_laddr: .dword */
|
||||||
0x00000000,
|
0x00000000,
|
||||||
/* fw_dyn: */
|
/* fw_dyn: */
|
||||||
|
|
Loading…
Reference in a new issue