target-m68k: move fmove CR to a function
Move code of fmove to/from control register to a function Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170620205121.26515-2-laurent@vivier.eu>
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@ -4099,6 +4099,35 @@ DISAS_INSN(trap)
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gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
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}
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static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
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uint32_t insn, uint32_t ext)
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{
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int mask = (ext >> 10) & 7;
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int is_write = (ext >> 13) & 1;
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TCGv val;
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switch (mask) {
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case 1: /* FPIAR */
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case 2: /* FPSR */
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default:
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qemu_log_mask(LOG_UNIMP, "Unimplemented: fmove to/from control %d",
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mask);
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goto undef;
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case 4: /* FPCR */
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if (is_write) {
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val = tcg_const_i32(0);
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DEST_EA(env, insn, OS_LONG, val, NULL);
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tcg_temp_free(val);
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}
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/* Not implemented. Ignore register update */
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break;
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}
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return;
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undef:
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s->pc -= 2;
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disas_undef_fpu(env, s, insn);
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}
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/* ??? FP exceptions are not implemented. Most exceptions are deferred until
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immediately before the next FP instruction is executed. */
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DISAS_INSN(fpu)
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@ -4177,32 +4206,9 @@ DISAS_INSN(fpu)
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tcg_temp_free_i32(tmp32);
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return;
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case 4: /* fmove to control register. */
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switch ((ext >> 10) & 7) {
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case 4: /* FPCR */
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/* Not implemented. Ignore writes. */
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break;
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case 1: /* FPIAR */
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case 2: /* FPSR */
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default:
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cpu_abort(NULL, "Unimplemented: fmove to control %d",
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(ext >> 10) & 7);
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}
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break;
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case 5: /* fmove from control register. */
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switch ((ext >> 10) & 7) {
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case 4: /* FPCR */
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/* Not implemented. Always return zero. */
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tmp32 = tcg_const_i32(0);
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break;
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case 1: /* FPIAR */
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case 2: /* FPSR */
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default:
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cpu_abort(NULL, "Unimplemented: fmove from control %d",
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(ext >> 10) & 7);
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goto undef;
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}
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DEST_EA(env, insn, OS_LONG, tmp32, NULL);
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break;
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gen_op_fmove_fcr(env, s, insn, ext);
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return;
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case 6: /* fmovem */
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case 7:
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{
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