tcg-aarch64: Support div, rem
Clean up multiply at the same time. For remainder, generic code will produce mul+sub, whereas we can implement with msub. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
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@ -313,6 +313,12 @@ typedef enum {
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I3508_RORV = 0x1ac02c00,
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I3508_RORV = 0x1ac02c00,
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I3508_SMULH = 0x9b407c00,
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I3508_SMULH = 0x9b407c00,
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I3508_UMULH = 0x9bc07c00,
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I3508_UMULH = 0x9bc07c00,
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I3508_UDIV = 0x1ac00800,
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I3508_SDIV = 0x1ac00c00,
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/* Data-processing (3 source) instructions. */
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I3509_MADD = 0x1b000000,
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I3509_MSUB = 0x1b008000,
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/* Logical shifted register instructions (without a shift). */
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/* Logical shifted register instructions (without a shift). */
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I3510_AND = 0x0a000000,
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I3510_AND = 0x0a000000,
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@ -467,6 +473,12 @@ static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,
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| tcg_cond_to_aarch64[c] << 12);
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| tcg_cond_to_aarch64[c] << 12);
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}
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}
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static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
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TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
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{
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tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
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}
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static inline void tcg_out_ldst_9(TCGContext *s,
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static inline void tcg_out_ldst_9(TCGContext *s,
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enum aarch64_ldst_op_data op_data,
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enum aarch64_ldst_op_data op_data,
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@ -595,14 +607,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
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arg, arg1, arg2);
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arg, arg1, arg2);
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}
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}
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static inline void tcg_out_mul(TCGContext *s, TCGType ext,
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TCGReg rd, TCGReg rn, TCGReg rm)
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{
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/* Using MADD 0x1b000000 with Ra = wzr alias MUL 0x1b007c00 */
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unsigned int base = ext ? 0x9b007c00 : 0x1b007c00;
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tcg_out32(s, base | rm << 16 | rn << 5 | rd);
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}
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static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
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static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
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TCGReg rn, unsigned int a, unsigned int b)
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TCGReg rn, unsigned int a, unsigned int b)
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{
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{
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@ -1395,7 +1399,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_mul_i64:
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case INDEX_op_mul_i64:
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case INDEX_op_mul_i32:
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case INDEX_op_mul_i32:
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tcg_out_mul(s, ext, a0, a1, a2);
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tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR);
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break;
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case INDEX_op_div_i64:
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case INDEX_op_div_i32:
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tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2);
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break;
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case INDEX_op_divu_i64:
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case INDEX_op_divu_i32:
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tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2);
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break;
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case INDEX_op_rem_i64:
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case INDEX_op_rem_i32:
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tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2);
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tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
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break;
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case INDEX_op_remu_i64:
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case INDEX_op_remu_i32:
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tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2);
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tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
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break;
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break;
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case INDEX_op_shl_i64:
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case INDEX_op_shl_i64:
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@ -1626,6 +1650,14 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
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{ INDEX_op_sub_i64, { "r", "r", "rA" } },
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{ INDEX_op_sub_i64, { "r", "r", "rA" } },
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{ INDEX_op_mul_i32, { "r", "r", "r" } },
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{ INDEX_op_mul_i32, { "r", "r", "r" } },
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{ INDEX_op_mul_i64, { "r", "r", "r" } },
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{ INDEX_op_mul_i64, { "r", "r", "r" } },
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{ INDEX_op_div_i32, { "r", "r", "r" } },
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{ INDEX_op_div_i64, { "r", "r", "r" } },
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{ INDEX_op_divu_i32, { "r", "r", "r" } },
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{ INDEX_op_divu_i64, { "r", "r", "r" } },
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{ INDEX_op_rem_i32, { "r", "r", "r" } },
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{ INDEX_op_rem_i64, { "r", "r", "r" } },
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{ INDEX_op_remu_i32, { "r", "r", "r" } },
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{ INDEX_op_remu_i64, { "r", "r", "r" } },
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{ INDEX_op_and_i32, { "r", "r", "rwL" } },
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{ INDEX_op_and_i32, { "r", "r", "rwL" } },
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{ INDEX_op_and_i64, { "r", "r", "rL" } },
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{ INDEX_op_and_i64, { "r", "r", "rL" } },
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{ INDEX_op_or_i32, { "r", "r", "rwL" } },
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{ INDEX_op_or_i32, { "r", "r", "rwL" } },
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@ -39,8 +39,8 @@ typedef enum {
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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/* optional instructions */
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 0
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 0
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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@ -64,8 +64,8 @@ typedef enum {
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_div_i64 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 0
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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