target-ppc: Add ISA2.06 bpermd Instruction
This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -1877,9 +1877,11 @@ enum {
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PPC2_ISA205 = 0x0000000000000020ULL,
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PPC2_ISA205 = 0x0000000000000020ULL,
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/* VSX additions in ISA 2.07 */
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/* VSX additions in ISA 2.07 */
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PPC2_VSX207 = 0x0000000000000040ULL,
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PPC2_VSX207 = 0x0000000000000040ULL,
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/* ISA 2.06B bpermd */
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PPC2_PERM_ISA206 = 0x0000000000000080ULL,
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#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
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#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
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PPC2_ISA205 | PPC2_VSX207)
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PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206)
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};
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};
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/*****************************************************************************/
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/*****************************************************************************/
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@ -41,6 +41,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
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DEF_HELPER_3(srad, tl, env, tl, tl)
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DEF_HELPER_3(srad, tl, env, tl, tl)
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#endif
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#endif
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@ -53,6 +53,26 @@ target_ulong helper_cntlzd(target_ulong t)
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}
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}
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#endif
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#endif
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#if defined(TARGET_PPC64)
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uint64_t helper_bpermd(uint64_t rs, uint64_t rb)
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{
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int i;
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uint64_t ra = 0;
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for (i = 0; i < 8; i++) {
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int index = (rs >> (i*8)) & 0xFF;
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if (index < 64) {
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if (rb & (1ull << (63-index))) {
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ra |= 1 << i;
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}
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}
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}
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return ra;
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}
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#endif
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target_ulong helper_cmpb(target_ulong rs, target_ulong rb)
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target_ulong helper_cmpb(target_ulong rs, target_ulong rb)
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{
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{
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target_ulong mask = 0xff;
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target_ulong mask = 0xff;
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@ -1524,6 +1524,15 @@ static void gen_prtyd(DisasContext *ctx)
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}
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}
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#endif
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#endif
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#if defined(TARGET_PPC64)
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/* bpermd */
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static void gen_bpermd(DisasContext *ctx)
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{
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gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
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cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
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}
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#endif
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#if defined(TARGET_PPC64)
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#if defined(TARGET_PPC64)
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/* extsw & extsw. */
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/* extsw & extsw. */
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GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
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GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
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@ -9433,6 +9442,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
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GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
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GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
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GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
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GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
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GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
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GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
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GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
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#endif
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#endif
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GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
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@ -4722,7 +4722,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
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PPC_FLOAT_STFIWX | PPC_WAIT |
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PPC_FLOAT_STFIWX | PPC_WAIT |
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PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
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PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
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PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
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PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
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pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
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pcc->msr_mask = 0x000000009402FB36ULL;
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pcc->msr_mask = 0x000000009402FB36ULL;
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pcc->mmu_model = POWERPC_MMU_BOOKE206;
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pcc->mmu_model = POWERPC_MMU_BOOKE206;
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pcc->excp_model = POWERPC_EXCP_BOOKE;
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pcc->excp_model = POWERPC_EXCP_BOOKE;
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@ -7068,7 +7068,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
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PPC_64B | PPC_ALTIVEC |
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PPC_64B | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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PPC2_PERM_ISA206;
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pcc->msr_mask = 0x800000000284FF37ULL;
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pcc->msr_mask = 0x800000000284FF37ULL;
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pcc->mmu_model = POWERPC_MMU_2_06;
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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@ -7106,7 +7107,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
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PPC_64B | PPC_ALTIVEC |
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PPC_64B | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
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pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
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PPC2_PERM_ISA206;
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pcc->msr_mask = 0x800000000204FF37ULL;
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pcc->msr_mask = 0x800000000204FF37ULL;
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pcc->mmu_model = POWERPC_MMU_2_06;
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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@ -7144,7 +7146,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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PPC_64B | PPC_ALTIVEC |
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PPC_64B | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD;
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PPC_POPCNTB | PPC_POPCNTWD;
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pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
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pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
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PPC2_PERM_ISA206;
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pcc->msr_mask = 0x800000000284FF36ULL;
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pcc->msr_mask = 0x800000000284FF36ULL;
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pcc->mmu_model = POWERPC_MMU_2_06;
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pcc->mmu_model = POWERPC_MMU_2_06;
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#if defined(CONFIG_SOFTMMU)
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#if defined(CONFIG_SOFTMMU)
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