target/ppc: Use non-arithmetic conversions for fp load/store
Memory operations have no side effects on fp state. The use of a "real" conversions between float64 and float32 would raise exceptions for SNaN and out-of-range inputs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -47,24 +47,61 @@ static inline bool fp_exceptions_enabled(CPUPPCState *env)
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/*****************************************************************************/
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/*****************************************************************************/
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/* Floating point operations helpers */
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/* Floating point operations helpers */
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uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
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{
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CPU_FloatU f;
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CPU_DoubleU d;
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f.l = arg;
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/*
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d.d = float32_to_float64(f.f, &env->fp_status);
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* This is the non-arithmatic conversion that happens e.g. on loads.
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return d.ll;
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* In the Power ISA pseudocode, this is called DOUBLE.
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*/
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uint64_t helper_todouble(uint32_t arg)
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{
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uint32_t abs_arg = arg & 0x7fffffff;
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uint64_t ret;
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if (likely(abs_arg >= 0x00800000)) {
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/* Normalized operand, or Inf, or NaN. */
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ret = (uint64_t)extract32(arg, 30, 2) << 62;
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ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
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ret |= (uint64_t)extract32(arg, 0, 30) << 29;
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} else {
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/* Zero or Denormalized operand. */
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ret = (uint64_t)extract32(arg, 31, 1) << 63;
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if (unlikely(abs_arg != 0)) {
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/* Denormalized operand. */
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int shift = clz32(abs_arg) - 9;
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int exp = -126 - shift + 1023;
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ret |= (uint64_t)exp << 52;
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ret |= abs_arg << (shift + 29);
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}
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}
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return ret;
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}
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}
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uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
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/*
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* This is the non-arithmatic conversion that happens e.g. on stores.
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* In the Power ISA pseudocode, this is called SINGLE.
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*/
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uint32_t helper_tosingle(uint64_t arg)
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{
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{
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CPU_FloatU f;
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int exp = extract64(arg, 52, 11);
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CPU_DoubleU d;
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uint32_t ret;
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d.ll = arg;
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if (likely(exp > 896)) {
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f.f = float64_to_float32(d.d, &env->fp_status);
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/* No denormalization required (includes Inf, NaN). */
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return f.l;
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ret = extract64(arg, 62, 2) << 30;
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ret |= extract64(arg, 29, 30);
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} else {
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/* Zero or Denormal result. If the exponent is in bounds for
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* a single-precision denormal result, extract the proper bits.
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* If the input is not zero, and the exponent is out of bounds,
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* then the result is undefined; this underflows to zero.
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*/
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ret = extract64(arg, 63, 1) << 31;
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if (unlikely(exp >= 874)) {
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/* Denormal result. */
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ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
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}
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}
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return ret;
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}
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}
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static inline int ppc_float32_get_unbiased_exp(float32 f)
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static inline int ppc_float32_get_unbiased_exp(float32 f)
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@ -61,8 +61,8 @@ DEF_HELPER_2(compute_fprf_float64, void, env, i64)
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DEF_HELPER_3(store_fpscr, void, env, i64, i32)
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DEF_HELPER_3(store_fpscr, void, env, i64, i32)
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DEF_HELPER_2(fpscr_clrbit, void, env, i32)
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DEF_HELPER_2(fpscr_clrbit, void, env, i32)
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DEF_HELPER_2(fpscr_setbit, void, env, i32)
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DEF_HELPER_2(fpscr_setbit, void, env, i32)
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DEF_HELPER_2(float64_to_float32, i32, env, i64)
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DEF_HELPER_FLAGS_1(todouble, TCG_CALL_NO_RWG_SE, i64, i32)
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DEF_HELPER_2(float32_to_float64, i64, env, i32)
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DEF_HELPER_FLAGS_1(tosingle, TCG_CALL_NO_RWG_SE, i32, i64)
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DEF_HELPER_4(fcmpo, void, env, i64, i64, i32)
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DEF_HELPER_4(fcmpo, void, env, i64, i64, i32)
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DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
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DEF_HELPER_4(fcmpu, void, env, i64, i64, i32)
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@ -660,15 +660,12 @@ GEN_LDUF(name, ldop, op | 0x21, type); \
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GEN_LDUXF(name, ldop, op | 0x01, type); \
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GEN_LDUXF(name, ldop, op | 0x01, type); \
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GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
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GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
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static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr)
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{
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{
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TCGv t0 = tcg_temp_new();
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TCGv_i32 tmp = tcg_temp_new_i32();
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
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gen_qemu_ld32u(ctx, t0, arg2);
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gen_helper_todouble(dest, tmp);
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tcg_gen_trunc_tl_i32(t1, t0);
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tcg_temp_free_i32(tmp);
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tcg_temp_free(t0);
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gen_helper_float32_to_float64(arg1, cpu_env, t1);
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tcg_temp_free_i32(t1);
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}
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}
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/* lfd lfdu lfdux lfdx */
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/* lfd lfdu lfdux lfdx */
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@ -836,15 +833,12 @@ GEN_STUF(name, stop, op | 0x21, type); \
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GEN_STUXF(name, stop, op | 0x01, type); \
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GEN_STUXF(name, stop, op | 0x01, type); \
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GEN_STXF(name, stop, 0x17, op | 0x00, type)
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GEN_STXF(name, stop, 0x17, op | 0x00, type)
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static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr)
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{
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{
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i32 tmp = tcg_temp_new_i32();
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TCGv t1 = tcg_temp_new();
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gen_helper_tosingle(tmp, src);
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gen_helper_float64_to_float32(t0, cpu_env, arg1);
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tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL));
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tcg_gen_extu_i32_tl(t1, t0);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(t0);
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gen_qemu_st32(ctx, t1, arg2);
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tcg_temp_free(t1);
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}
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}
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/* stfd stfdu stfdux stfdx */
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/* stfd stfdu stfdux stfdx */
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