target/s390x: Use tcg_gen_gvec_dup_imm
The gen_gvec_dupi switch is unnecessary with the new function. Replace it with a local gen_gvec_dup_imm that takes care of the register to offset conversion and length arguments. Drop zero_vec and use use gen_gvec_dup_imm with 0. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -231,8 +231,8 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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#define gen_gvec_mov(v1, v2) \
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tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
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16)
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#define gen_gvec_dup64i(v1, c) \
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tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
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#define gen_gvec_dup_imm(es, v1, c) \
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tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
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#define gen_gvec_fn_2(fn, es, v1, v2) \
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tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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16, 16)
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@ -316,31 +316,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
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tcg_temp_free_i64(cl);
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}
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static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
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{
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switch (es) {
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case ES_8:
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tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
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break;
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case ES_16:
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tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
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break;
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case ES_32:
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tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
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break;
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case ES_64:
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gen_gvec_dup64i(reg, c);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static void zero_vec(uint8_t reg)
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{
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tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
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}
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static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
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uint64_t b)
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{
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@ -396,8 +371,8 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
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* Masks for both 64 bit elements of the vector are the same.
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* Trust tcg to produce a good constant loading.
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*/
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gen_gvec_dup64i(get_field(s, v1),
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generate_byte_mask(i2 & 0xff));
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gen_gvec_dup_imm(ES_64, get_field(s, v1),
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generate_byte_mask(i2 & 0xff));
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} else {
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TCGv_i64 t = tcg_temp_new_i64();
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@ -432,7 +407,7 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
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}
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}
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gen_gvec_dupi(es, get_field(s, v1), mask);
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gen_gvec_dup_imm(es, get_field(s, v1), mask);
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return DISAS_NEXT;
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}
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@ -585,7 +560,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
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t = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
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zero_vec(get_field(s, v1));
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gen_gvec_dup_imm(es, get_field(s, v1), 0);
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write_vec_element_i64(t, get_field(s, v1), enr, es);
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tcg_temp_free_i64(t);
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return DISAS_NEXT;
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@ -892,7 +867,7 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
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return DISAS_NORETURN;
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}
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gen_gvec_dupi(es, get_field(s, v1), data);
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gen_gvec_dup_imm(es, get_field(s, v1), data);
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return DISAS_NEXT;
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}
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@ -1372,7 +1347,7 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
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read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
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tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
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}
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zero_vec(get_field(s, v1));
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gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
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write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
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tcg_temp_free_i32(tmp);
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