target/arm: Use tcg_gen_gvec_dup_imm
In a few cases, we're able to remove some manual replication. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -502,7 +502,7 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
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tcg_temp_free_i64(tcg_zero);
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}
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if (vsz > 16) {
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tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);
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tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
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}
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}
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@ -7785,8 +7785,8 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
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if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
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/* MOVI or MVNI, with MVNI negation handled above. */
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tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
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vec_full_reg_size(s), imm);
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tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), is_q ? 16 : 8,
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vec_full_reg_size(s), imm);
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} else {
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/* ORR or BIC, with BIC negation to AND handled above. */
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if (is_neg) {
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@ -10214,8 +10214,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
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if (is_u) {
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if (shift == 8 << size) {
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/* Shift count the same size as element size produces zero. */
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tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),
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is_q ? 16 : 8, vec_full_reg_size(s), 0);
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tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd),
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is_q ? 16 : 8, vec_full_reg_size(s), 0);
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} else {
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gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);
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}
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@ -177,7 +177,7 @@ static bool do_mov_z(DisasContext *s, int rd, int rn)
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static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
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{
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unsigned vsz = vec_full_reg_size(s);
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tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), vsz, vsz, word);
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tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
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}
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/* Invoke a vector expander on two Pregs. */
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@ -1453,7 +1453,7 @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
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unsigned oprsz = size_for_gvec(setsz / 8);
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if (oprsz * 8 == setsz) {
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tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
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tcg_gen_gvec_dup_imm(MO_64, ofs, oprsz, maxsz, word);
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goto done;
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}
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}
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@ -2044,7 +2044,7 @@ static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a)
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unsigned nofs = vec_reg_offset(s, a->rn, index, esz);
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tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz);
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} else {
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tcg_gen_gvec_dup64i(dofs, vsz, vsz, 0);
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tcg_gen_gvec_dup_imm(esz, dofs, vsz, vsz, 0);
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}
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}
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return true;
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@ -3260,9 +3260,7 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
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/* Decode the VFP immediate. */
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imm = vfp_expand_imm(a->esz, a->imm);
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imm = dup_const(a->esz, imm);
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tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm);
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tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, imm);
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}
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return true;
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}
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@ -3276,7 +3274,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
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unsigned vsz = vec_full_reg_size(s);
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int dofs = vec_full_reg_offset(s, a->rd);
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tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm));
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tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
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}
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return true;
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}
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@ -5209,7 +5209,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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MIN(shift, (8 << size) - 1),
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vec_size, vec_size);
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} else if (shift >= 8 << size) {
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tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
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tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size,
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vec_size, 0);
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} else {
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tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift,
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vec_size, vec_size);
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@ -5260,7 +5261,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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* architecturally valid and results in zero.
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*/
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if (shift >= 8 << size) {
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tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0);
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tcg_gen_gvec_dup_imm(size, rd_ofs,
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vec_size, vec_size, 0);
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} else {
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tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
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vec_size, vec_size);
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@ -5606,7 +5608,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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}
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tcg_temp_free_i64(t64);
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} else {
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tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm);
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tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size,
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vec_size, imm);
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}
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}
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}
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