target/arm: Don't do raw writes for PMINTENCLR
Raw writes to this register when in KVM mode can cause interrupts to be raised (even when the PMU is disabled). Because the underlying state is already aliased to PMINTENSET (which already provides raw write functions), we can safely disable raw accesses to PMINTENCLR entirely. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Message-id: 20200707152616.1917154-1-aaron@os.amperecomputing.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2269,13 +2269,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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.resetvalue = 0x0 },
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.resetvalue = 0x0 },
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{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
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{ .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_tpm,
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.access = PL1_RW, .accessfn = access_tpm,
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.type = ARM_CP_ALIAS | ARM_CP_IO,
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.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.writefn = pmintenclr_write, },
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.writefn = pmintenclr_write, },
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{ .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
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{ .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
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.opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
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.access = PL1_RW, .accessfn = access_tpm,
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.access = PL1_RW, .accessfn = access_tpm,
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.type = ARM_CP_ALIAS | ARM_CP_IO,
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.type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
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.writefn = pmintenclr_write },
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.writefn = pmintenclr_write },
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{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
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{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
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