target/ppc: Refactor emulation of vmrgew and vmrgow instructions
Since I found this two instructions implemented with tcg, I refactored them so they are consistent with other similar implementations that I introduced in this patch. Also, a new dual macro GEN_VXFORM_TRANS_DUAL is added. This macro is used if one instruction is realized with direct translation, and second one with a helper. Signed-off-by: Stefan Brankovic <stefan.brankovic@rt-rk.com> Message-Id: <1566898663-25858-4-git-send-email-stefan.brankovic@rt-rk.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -350,6 +350,28 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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} \
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}
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/*
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* We use this macro if one instruction is realized with direct
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* translation, and second one with helper.
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*/
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#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
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static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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{ \
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if ((Rc(ctx->opcode) == 0) && \
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((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
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if (unlikely(!ctx->altivec_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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} \
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trans_##name0(ctx); \
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} else if ((Rc(ctx->opcode) == 1) && \
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((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
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gen_##name1(ctx); \
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} else { \
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
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} \
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}
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/* Adds support to provide invalid mask */
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#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
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name1, flg1, flg2_1, inval1) \
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@ -431,20 +453,13 @@ GEN_VXFORM(vmrglb, 6, 4);
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GEN_VXFORM(vmrglh, 6, 5);
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GEN_VXFORM(vmrglw, 6, 6);
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static void gen_vmrgew(DisasContext *ctx)
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static void trans_vmrgew(DisasContext *ctx)
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{
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TCGv_i64 tmp;
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TCGv_i64 avr;
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int VT, VA, VB;
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if (unlikely(!ctx->altivec_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VPU);
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return;
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}
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VT = rD(ctx->opcode);
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VA = rA(ctx->opcode);
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VB = rB(ctx->opcode);
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tmp = tcg_temp_new_i64();
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avr = tcg_temp_new_i64();
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int VT = rD(ctx->opcode);
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int VA = rA(ctx->opcode);
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int VB = rB(ctx->opcode);
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TCGv_i64 tmp = tcg_temp_new_i64();
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TCGv_i64 avr = tcg_temp_new_i64();
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get_avr64(avr, VB, true);
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tcg_gen_shri_i64(tmp, avr, 32);
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@ -462,21 +477,14 @@ static void gen_vmrgew(DisasContext *ctx)
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tcg_temp_free_i64(avr);
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}
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static void gen_vmrgow(DisasContext *ctx)
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static void trans_vmrgow(DisasContext *ctx)
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{
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TCGv_i64 t0, t1;
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TCGv_i64 avr;
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int VT, VA, VB;
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if (unlikely(!ctx->altivec_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VPU);
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return;
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}
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VT = rD(ctx->opcode);
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VA = rA(ctx->opcode);
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VB = rB(ctx->opcode);
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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avr = tcg_temp_new_i64();
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int VT = rD(ctx->opcode);
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int VA = rA(ctx->opcode);
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int VB = rB(ctx->opcode);
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 avr = tcg_temp_new_i64();
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get_avr64(t0, VB, true);
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get_avr64(t1, VA, true);
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@ -936,14 +944,14 @@ GEN_VXFORM_ENV(vminfp, 5, 17);
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GEN_VXFORM_HETRO(vextublx, 6, 24)
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GEN_VXFORM_HETRO(vextuhlx, 6, 25)
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GEN_VXFORM_HETRO(vextuwlx, 6, 26)
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GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
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GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
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vextuwlx, PPC_NONE, PPC2_ISA300)
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GEN_VXFORM_HETRO(vextubrx, 6, 28)
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GEN_VXFORM_HETRO(vextuhrx, 6, 29)
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GEN_VXFORM_HETRO(vextuwrx, 6, 30)
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GEN_VXFORM_TRANS(lvsl, 6, 31)
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GEN_VXFORM_TRANS(lvsr, 6, 32)
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GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
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GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
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vextuwrx, PPC_NONE, PPC2_ISA300)
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#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
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